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| high performance microcontrollers zneo ? Z16F series copyright ?2009 by zilog ? , inc. all rights reserved. www.zilog.com ps022007-0109 product specification www.datasheet.net/ datasheet pdf - http://www..co.kr/
ps022007-0109 p r e l i m i n a r y disclaimer zneo ? Z16F series product specification ii do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2009 by zilog, inc. all rights reserved. information in this pu blication concerning the devices, applications, or technology describe d is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical an d mechanical engineering. z8, z8 encore!, zneo, and Z16F are trademarks or registered trademarks of zilog, inc. all other product or service names are the property of their respective owners. warning: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary revision history zneo ? Z16F series product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, refer to the corresponding pages or appropriate links given in the table below. date revision level section description page no january 2009 07 timer 0-2 control 0 register analog functions electrical characteristics internal precision oscillator ta b l e 62 , added ?only counter mode should be used with this feature? to bit 4 description. adc overview , updated fast conversion time to 2.5 s. updated ta b l e 182 . removed reference to 32 khz. 108 244 337 335 february 2007 06 independent and complementary pwm outputs corrected pwm registers. updated figure 22. 118 electrical characteristics replaced 105c with 125 c in ta b l e 182 through ta b l e 189 . added figure 72 , figure 73 , and figure 74 . 337 i 2 c master/slave controller changes to software control of i 2 c transactions section. 209 packaging updated part number suffix designations section. 363 enhanced serial peripheral interface throughput section modified. 180 july 2006 05 external interface , general-purpose input/ output , dma controller , option bits , on-chip debugger , and electrical characteristics modifications done in the following chapters: external interface, gpio, dma controller, option bits, on-chip debugger, and electrical characteristics. 39, 68, 267, 293,299 and 337 ordering information ordering information modified. 360 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary revision history zneo ? Z16F series product specification iv january 2006 04 all changed zneo to zneo in the entire document. all all added tm symbol to zneo. all signal and pin descriptions , interrupt controller , and analog functions modifications done to following chapters: pin description, interrupt controller and analog functions. 7 , 80 , and 243 ordering information ordering information modified. 360 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification iv table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 zneo cpu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 random access memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 zneo peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10-bit analog-to-digital converter with programmable gain amplifier . . . . . 4 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . 4 infrared encoder/decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 inter-integrated circuit master/slave controller . . . . . . . . . . . . . . . . . . . . . . 4 enhanced serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pulse width modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 standard timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 internal non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 internal ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 input/output memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification v input/output memory precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 cpu control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 bus widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 peripheral address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 external interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 chip selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 tools compatibility guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 external wait pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 wait state generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 isa-compatible mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 external interface control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . 44 external interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 chip select control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 external interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 external interface write timing - normal mode . . . . . . . . . . . . . . . . . . . . . 48 external interface write timing - isa mode . . . . . . . . . . . . . . . . . . . . . . . . 50 external interface read timing - normal mode . . . . . . . . . . . . . . . . . . . . . 52 external interface read timing - isa mode . . . . . . . . . . . . . . . . . . . . . . . . 55 reset and stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 voltage brownout reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 external reset indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 user reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 fault detect logic reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 stop mode recovery using wdt time-out . . . . . . . . . . . . . . . . . . . . . . . . 63 stop mode recovery using a gpio port pin transition . . . . . . . . . . . . . . . 63 reset status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification vi low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 peripheral-level power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 power control option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 port a-k input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 port a-k output data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 port a-k data direction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 port a-k high drive enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 port a-k alternate function high and low registers . . . . . . . . . . . . . . . . . 75 port a-k output control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 port a-k pull-up enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 port a-k stop mode recovery source enable registers . . . . . . . . . . . . . . 77 port a irq mux1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 port a irq mux register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 port a irq edge register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 port c irq mux register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 system exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 system exception status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 last irq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification vii irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 90 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 92 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 93 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 reading timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 timer 0-2 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . 106 timer x reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . 107 timer 0-2 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . 108 timer 0-2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 multi-channel pwm timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 pwm option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 pwm reload event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 pwm prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 pwm period and count resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 pwm duty cycle registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 independent and complementary pwm outputs . . . . . . . . . . . . . . . . . . . 118 manual off-state control of pwm output channels . . . . . . . . . . . . . . . . . 119 deadband insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 minimum pwm pulse width filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 synchronization of pwm and adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 synchronized current-sense sample and hold . . . . . . . . . . . . . . . . . . . . 120 pwm timer and fault interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 fault detection and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 pwm operation in cpu halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 pwm operation in cpu stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 observing the state of pwm output channels . . . . . . . . . . . . . . . . . . . . . 121 pwm control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 pwm reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . 122 pwm 0-2 duty cycle high and low byte registers . . . . . . . . . . . . . . . . . 123 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification viii pwm control 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 pwm control 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 pwm deadband register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 pwm minimum pulse width filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 pwm fault mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 pwm fault status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 pwm fault control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pwm input sample register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 pwm output control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 current-sense sample and hold control registers . . . . . . . . . . . . . . . . . 132 lin-uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 data format for standard uart modes . . . . . . . . . . . . . . . . . . . . . . . . . . 136 transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . 136 transmitting data using interrupt-driven method . . . . . . . . . . . . . . . . . . . 137 receiving data using polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 receiving data using the interrupt-driven method . . . . . . . . . . . . . . . . . . 139 clear to send operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 lin-uart special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 lin protocol mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 lin-uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 lin-uart dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 lin-uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 lin-uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 lin-uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 lin-uart receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 lin-uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 lin-uart mode select and status register . . . . . . . . . . . . . . . . . . . . . . 157 lin-uart control 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 lin-uart control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification ix lin-uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 lin-uart baud rate high and low byte registers . . . . . . . . . . . . . . . . 164 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 infrared encoder/decoder control register definitions . . . . . . . . . . . . . . . . . 174 enhanced serial peripheral interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 espi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 master-in/slave-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 master-out/slave-in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 slave select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 espi register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 comparison with basic spi block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 espi clock phase and polarity control . . . . . . . . . . . . . . . . . . . . . . . . . . 180 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 spi protocol configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 espi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 espi baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 espi control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 espi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 espi transmit data command register . . . . . . . . . . . . . . . . . . . . . . . . . . 192 espi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 espi mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 espi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 espi state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 espi baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . 200 i 2 c master/slave controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification x i 2 c master/slave controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 comparison with master mode only i 2 c controller . . . . . . . . . . . . . . . . . . 205 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 sda and scl signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 i 2 c interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 software control of i 2 c transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 master transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 slave transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 dma control of i 2 c transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 i 2 c control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 i 2 c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 i 2 c interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 i 2 c control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 i 2 c baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 230 i 2 c state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 i 2 c mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 i 2 c slave address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 watchdog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 watchdog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 watchdog timer reload unlock sequence . . . . . . . . . . . . . . . . . . . . . . . 241 watchdog timer register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 watchdog timer reload high and low byte registers . . . . . . . . . . . . . . 242 analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 adc overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 adc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 adc interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 adc0 timer0 capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 adc convert on read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 reference buffer, rbuf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 internal voltage reference generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification xi adc0 control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 adc0 data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 adc0 data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 sample settling time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 sample time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 adc clock prescale register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 adc0 max register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 adc timer0 capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 comparator and operational amplif ier overview . . . . . . . . . . . . . . . . . . . . . . 253 comparator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 operational amplifier operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 comparator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 comparator and operational amplifier control register . . . . . . . . . . . . . . 255 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 timing using the flash frequency register . . . . . . . . . . . . . . . . . . . . . . 259 flash read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 flash controller behavior us ing the on-chip debugger . . . . . . . . . . . . . . 262 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 flash command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 flash frequency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 dma features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 dma block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 dma description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification xii dma register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 dma control bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 dma water mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 dma peripheral interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 buffer closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 dma modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 linked list mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 dma priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 dma interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 dma request select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 dma control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 dma control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 dma x transfer length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 dma destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 dma source address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 dma list address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 external dma signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 program memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 program memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 program memory address 0002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 program memory address 0003h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 ipo trim registers (information area address 0021h and 0022h) . . . . . . 297 adc reference voltage trim (information area address 0023h) . . . . . . 298 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 on-chip debug enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification xiii auto-baud detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 9-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 start bit flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 initialization during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 debug lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 error reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 debug halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 reading and writing memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 reading memory crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 instruction trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 cyclic redundancy check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 memory cyclic redundancy check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 dbg pin used as a gpio pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 baud rate reload register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 line control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 hardware breakpoint registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 trace control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 trace address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 oscillator operation with an exte rnal rc network . . . . . . . . . . . . . . . . . . . . . 329 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y table of contents zneo ? Z16F series product specification xiv oscillator control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 system clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 clock selection following system reset . . . . . . . . . . . . . . . . . . . . . . . . . 332 clock failure detection and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 oscillator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 oscillator control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 oscillator divide register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . 343 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 general purpose i/o port input data sample timing . . . . . . . . . . . . . . . . 349 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 pre-characterization product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y introduction zneo ? Z16F series product specification 1 introduction zilog?s zneo ? Z16F family of products are op timized for demanding applications. the zneo line of zilog ? microcontroller products are based on the new zneo cpu. features zneo family of products in clude the following features: ? 20 mhz zneo cpu ? 128 kb internal flash memory with 16 -bit access and in-circuit programming (icp) ? 4 kb internal ram with 16-bit access ? external interface allows seamless conn ection to external data memory and peripheral with: ? six chip selects with programmable wait states ? 24-bit address bus supports 16 mb ? selectable 8-bit or 16-bit data bus widths ? programmable chip select signal polarity ? isa-compatible mode ? 12-channel, 10-bit analog-to-digital converter (adc) ? operational amplifier ? analog comparator ? 4-channel direct memory access (dma) controller supports internal or external dma requests ? two full-duplex 9-bit universal asynchro nous receiver/transmitter (uarts) with support for local interconnect network (lin) and infrared da ta association (irda) ? internal precision oscillator (ipo) ? inter-integrated circuit (i 2 c) master/slave controller ? enhanced serial peripheral interface (espi) ? 12-bit pulse width modulation (pwm) module with three complementary pairs or six independent pwm outputs with deadband generation and fault trip input ? three standard 16-bit timers with ca pture, compare, and pwm capability ? watchdog timer (wdt) with internal rc oscillator ? 76 general-purpose input/output (gpio) pins www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y introduction zneo ? Z16F series product specification 2 ? 24 interrupts with programmable priority ? on-chip debugger (ocd) ? voltage brownout (vbo) protection ? power-on reset (por) ? 2.7 v to 3.6 v operating voltage with 5 v-tolerant inputs ? 0 c to +70 c standard temperature and ? 40 c to +105 c ex tended temperature operating ranges block diagram figure 1 displays the architecture of the zneo ? Z16F series . figure 1. zneo Z16F series block diagram gpio with external interface (address and data bus) irda uarts i 2 c timers espi analog flash flash controller ram ram controller memory interrupt controller on-chip debugger zneo cpu wdt with rc oscillator por/vbo and reset controller oscillators (xtal, ipo) memory buses system clock dma pwm (3) (2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y introduction zneo ? Z16F series product specification 3 zneo cpu features zilog?s zneo ? cpu meets the continuing demand fo r faster and more code-efficient microcontrollers. the zneo cpu features are as follows: ? 16 mb of program memory address space for object code and data with 8-bit or 16-bit data paths. ? 8-bit, 16-bit, and 32-bit alu operations. ? 24-bit stack with overflow protection. ? direct register-to-register architecture allo ws each memory address to function as an accumulator. this improves execution tim e and decreases the required program memory. ? new instructions improve execution efficien cy for code developed using higher-level programming languages including ?c?. ? pipelined instructions: fe tch, decode, and execute. for more information on zneo cpu, refer to zneo cpu user manual (um0188) available for download at www.zilog.com . external interface the external interface allows seamless connection to external memory and peripherals. a 24-bit address bus and a selectable 8-bit or 16-bit data bus allows parallel access up to 16 mb. the programmable nature of the external interface supports connection to various bus styles. more gpio pins are utilized by co ntrolling address and control signals bitwise. flash controller the zneo products contain 128 kb of in ternal flash memory. the flash controller programs and erases the flash memory. zneo cpu accesses 16-bits at a time of internal flash memory to improve the processor throughput. a sector protection scheme allows flexible protection of user code. random access memory an internal ram of 4 kb provides storage sp ace for data, variables, and stack operations. like flash memory, zneo cpu accesses 16-bits at a time of internal ram to improve the processor performance. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y introduction zneo ? Z16F series product specification 4 zneo peripheral overview zilog?s zneo peripherals are briefly described below. 10-bit analog-to-digital converter with programmable gain amplifier the adc converts an analog input signal to a 10-bit binary number. the adc accepts inputs from 12 different analog input sources. analog comparator it features an on-chip analog comp arator with external input pins. operational amplifier it features a two-input, one-output operational amplifier. general-purpose input/output the zneo features 76 gpio pins. each pin is individually programmable. universal asynchronous receiver/transmitter it contains two fully-featured uarts with lin protocol support. the uart communication is full-duplex an d capable of handling asynchronous data transfers. the uarts support 8-bit and 9-bit data modes, selectable parity, and an efficient bus transceiver driver enable signal for controllin g a multi-transceiver bus, such as rs-485. infrared encoder/decoders the zneo Z16F series products contain tw o fully-functional, high-performance uart to infrared encoder/decoders (e ndecs). each infrared endec is integrated with an on-chip uart to allow easy communication betwee n the zneo Z16F series device and irda physical layer specification version 1.3- compliant infrared transceivers. infrared communication provides secure, reliable, lo w-cost, and point-to-p oint communication between pcs, pdas, cell phones, printers , and other infrared enabled devices. inter-integrated circui t master/slave controller the i 2 c controller makes Z16F2811 compatible with the i 2 c protocol. it consists of two bidirectional bus lines, a serial data (sda) line, and a serial clock (scl) line. the i 2 c operates as a master and/or slave and supports multi-master bus arbitration. enhanced serial peripheral interface the espi allows the data ex change between zneo Z16F series and other peripheral devices such as electrically erasable programm able read-only memory (eeproms), adcs, and integrated service digital networ k (isdn) devices. the sp i is a full-duplex, synchronous, character-oriented chan nel which supports a four-wire interface. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y introduction zneo ? Z16F series product specification 5 dma controller the zneo features a 4-channel dma for efficient transfer of data between peripherals and/or memories. the dma controller supports data transfers to and from both internal and external devices. pulse width modulator the zneo features a flexible pwm module with three complementary pairs or six independent pwm outputs supporting deadband operation and fault protection trip input. these features provide multiphase control capability for a variety of motor types and ensure safe operation of the motor by providing immediate shutdown of the pwm pins during fault condition. standard timers three 16-bit reloadable timers are used fo r timing/counting events and pwm signal generation. these timers provide a 16-bit programmable reload counter and operate in one-shot, continuous, gated, capture, compare, capture and compare, and pwm modes. the pwm function provides two complementary output signals with programmab le dead-time insertion. interrupt controller the zneo products support three levels of pr ogrammable interrupt priority. the interrupt sources include internal peripherals, gpio pins, and system fault detection. crystal oscillator the on-chip crystal oscillator features programm able gain to support crystals and ceramic resonators from 32 khz to 20 mh z. the oscillator is also used with external rc networks or clock drivers. reset controller the zneo is reset using the reset pin, por, wdt, stop mode recovery, or vbo warning signal. the bidirectional reset pin also provides a system reset output indicator. on-chip debugger the zneo Z16F series features an integrat ed ocd. the ocd provides a rich-set of debugging capabilities, such as reading and writing memo ry, programming the flash, setting breakpoints, and executing code. a sing le-pin interface prov ides communication to the ocd. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y introduction zneo ? Z16F series product specification 6 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 7 signal and pin descriptions the zneo ? Z16F series products are available in various package styles and pin configurations. this chapter describes the signals and available pin configurations for each package style. for more information on the physical package specifications, see packaging on page 357. available packages table 1 lists the package styles available for e ach device within the zneo Z16F series product line. pin configurations figure 2 through figure 5 displays the configur ations of all the pack ages available in the zneo Z16F series. for descri ption of each signal, see table 2 on page 12. table 1. zneo Z16F series package options part number 64-pin lqfp 68-pin plcc 80-pin qfp 100-pin lqfp Z16F2811 x x Z16F2810 x x x Z16F6411 x x Z16F3211 x x note : Z16F2810 does not have an external bus interface. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 8 figure 2. Z16F2810 in 64-pin low-profile quad flat package (lqfp) pa7 / sda pd6 / cts1 pc3 / sck pd7 / pwml2 vss pe5 pe6 pe7 vdd pa0 / t0in/t0out pd2 / pwmh2 pc2 / ss reset vdd pe4 pe3 vss pe2 49 32 pg3 pe1 vdd pe0 pa1 / t0out pa2 / de0 / faulty pa3 / cts0 / fault0 vss vdd pf7 pc5 / miso pd4 / rxd1 pd5 / txd1 pc4 / mosi vss pb1 / ana1 / t0in1 pb0 / ana0 / t0in0 avdd ph0 / ana8 ph1 / ana9 pb4 / ana4 pb7 / ana7 / opinn pb6 / ana6 / opinp / cinn pb5 / ana5 pb3 / ana3 / opout 48 1 pc7 / t2out / pwml0 pc6 / t2in/t2out / pwmh0 dbg pc1 / t1out / compout pc0 / t1in/t1out / cinn 17 pb2 / ana2 / t0in2 vref ph3 / ana11/cpinp ph2 / ana10 avss 16 vss pd1 / pwml1 pd0 / pwmh1 xout xin 64 pd3 / de1 vdd pa4 / rxd0 pa5 / txd0 pa6 / scl 33 vss 56 40 25 8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 9 figure 3. Z16F2810 in 68-pin plastic leaded chip carrier (plcc) pa7 / sda pd6 / cts1 pc3 / sck pd7 / pwml2 vss pe5 pe6 pe7 vdd pa0 / t0in/t0out pd2 / pwmh2 pc2 / ss reset vdd pe4 pe3 vss pe2 10 60 pg3 pe1 vdd pe0 pa1 / t0out pa2 / de0 / faulty pa3 / cts0 / fault0 vss vdd pf7 pc5 / miso pd4 / rxd1 pd5 / txd1 pc4 / mosi vss pb1 / ana1 / t0in1 pb0 / ana0 / t0in0 avdd ph0 / ana8 pb4 / ana4 pb7 / ana7 / opinn / cinn pb6 / ana6 / opinp pb5 / ana5 pb3 / ana3 / opout 9 27 pc7 / t2out / pwml0 pc6 / t2in/t2out / pwmh dbg pc1 / t1out / compout pc0 / t1in/t1out / cinn pb2 / ana2 / t0in2 vref ph3 / ana11 / cpinp ph2 / ana10 avss vss vdd pd1 / pwml1 pd0 / pwmh1 xout pd3 / de1 vss pa4 / rxd0 pa5 / txd0 vdd ph1 / ana9 pa6 / scl 61 vss 44 avss 43 xin 26 1 vdd 18 35 52 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 10 figure 4. zneo Z16F series in 80-pin quad flat package (qfp) 1 64 80 25 pa6 / scl 65 40 41 24 5 10 15 20 30 35 45 50 55 60 70 75 pd2 / pwmh2 / adr22 pc2 / ss / cs4 pf6 / adr6 reset vdd pf5 / adr5 pf4 / adr4 pf3 / adr3 pe4 / data4 pe3 / data3 vss pe2 / data2 pe1 / data1 pe0 / data0 vss pf2 / adr2 pf1 / adr1 pf0 / adr0 vdd pd1 / pwml1 / adr21 pd0 / pwmh1 / adr20 xout xin pa0 / t0in/t0out / dma0req pa7 / sda / cs4 pd6 / cts1 / adr17 pc3 / sck / dma2req pd7 / pwml2 / adr23 pg0 / adr8 vss pg1 / adr9 pg2 / adr10 pe5 / data5 pe6 / data6 pe7 / data7 vdd pg3 / adr11 pg4 / adr12 pg5 / adr13 pg6 / adr14 vdd pg7 / adr15 pc7 / t2out / pwml0 pc6 / t2in/t2out / pwmh0 dbg pc1 / t1out / dma1ack/ compout pc0 / t1in/t1out / dma1req/ cinn vss vss pb1 / ana1 / t0in1 pb0 / ana0 / t0in0 avdd ph0 / ana8 / wr pb4 / ana4 pb7 / ana7 / opinn pb6 / ana6 / opinp / cinn pb5 / ana5 pb3 / ana3 / opout pb2 / ana2 / t0in2 vref ph3 / ana11/cpinp / wait ph2 / ana10 / cs0 avss ph1 / ana9 / rd pa1 / t0out / dma0ack pa2 / de0 / faulty pa3 / cts0 / fault0 vss vdd pf7 / adr7 pc5 / miso / cs5 pd4 / rxd1 / adr18 pd5 / txd1 / adr19 pc4 / mosi / dma2ack pd3 / de1 / adr16 vss pa4 / rxd0 / cs1 pa5 / txd0 / cs2 vdd www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 11 figure 5. zneo Z16F series in 100-pin low-profile quad flat package (lqfp) pa7 / sda / cs4 pd6 / cts1 / adr17 pc3 / sck / dma2req pd7 / pwml2 / adr23 pg0 / adr8 vss pg1 / adr9 pg2 / adr10 pe5 / data5 pa0 /t0in/t0out / dma0req pd2 / pwmh2 / adr22 pc2 / ss / cs4 pf6 / adr6 reset vdd pf5 / adr5 pf4 / adr4 pf3 / adr3 1 75 pe6 / data6 pe4 / data4 pe7 / data7 pe3 / data3 pa1 / t0out / dma0ack pa2 / de0 / faulty pa3 / cts0 / fault0 vss vdd pf7 / adr7 pc5 / miso / cs5 pd4 / rxd1 / adr18 pd5 / txd1 / adr19 pc4 / mosi / dma2ack vdd pb1 / ana1 / t0in1 pb0 / ana0 / t0in0 avdd ph0 / ana8 / wr pb4 / ana4 pb7 / ana7 / opinn pb6 / ana6 / opinp / cinn pb5 / ana5 pb3 / ana3 / opout 95 26 vdd pg3 / adr11 pg4 / adr12 pg5 / adr13 pg6 / adr14 pb2 / ana2 / t0in2 vref ph3 / ana11/cpinp / wait ph2 / ana10 / cs0 avss vss pe2 / data2 pe1 / data1 pe0 / data0 vss pd3 / de1 / adr16 vss pj5 / data13 pj6 / data14 pj7 / data15 pj4 / data12 ph1 / ana9 / rd 80 vdd 40 pf2 / adr2 pg7 / adr15 pf1 / adr1 pc7 / t2out / pwml0 pc6 / t2in/t2out / pwmh0 dbg pc1 / t1out / dma1ack/ compout pc0 / t1in/t1out / dma1req/ cinn pf0 / adr0 vdd pd1 / pwml1 / adr21 pd0 / pwmh1 / adr20 xout vss 51 xin 25 5 10 15 20 30 35 55 60 65 70 85 90 pj0 / data8 pj1 / data9 pj2 / data10 pj3 / data11 100 vss pa4 / rxd0 / cs1 pa5 / txd0 / cs2 vdd 76 pk3 / cs1 pk2 / cs0 pk1 / blen pk0 / bhen pk6 / cs4 pk5 / cs3 pk4 / cs2 pk7 / cs5 vss pa6 / scl / cs3 45 vdd 50 vdd www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 12 signal descriptions table 2 describes the zneo signals. to determin e the signals available for the specific package styles, see pin configurations on page 7. most of the signals described in table 2 are multiplexed with gpio pins. these signals are available as alternate functions on the gpio pins. for more details on the gpio alternate functions, see general-purpose input/ output on page 68. table 2. signal descriptions signal mnemonic i/o description general-purpose input/output ports a?k pa[7:0] i/o port a[7:0] : these pins are used for gpio pb[7:0] i/o port b[7:0] : these pins are used for gpio pc[7:0] i/o port c[7:0] : these pins are used for gpio pd[7:0] i/o port d[7:0] : these pins are used for gpio pe[7:0] i/o port e[7:0] : these pins are used for gpio pf[7:0] i/o port f[7:0] : these pins are used for gpio pg[7:0] i/o port g[7:0] : these pins are used for gpio ph[3:0] i/o port h[3:0] : these pins are used for gpio pj[7:0] i/o port j[7:0] : these pins are used for gpio pk[7:0] i/o port k[7:0] : these pins are used for gpio external interface adr[23:0] o address bus : when the associated gpio pins are configured for alternate function and the external interface is enabled, these pins function as output pin only. the address bus signals are driven to 0, when execution is out of inte rnal program memory. the address bus alternate functions are individually enabled and disabled. data[15:0] i/o data bus : when the associated gpio pins are configured for alternate function and the external interface is enabled, these pins functions as input/output. the data bus alternate functions are individually enabled and disabled. when write operation is not performed through the external interface, these signals are tri- stated. the data bus is enabled as either 8-bits (data[7:0] only) or 16-bits (data[15:0]). rd o read output : this pin is the read output signal from the external interface. assertion of the rd signal indicates that the zneo cpu is performing a read operation from the external memory or peripheral. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 13 wr o write output : this pin is the write output signal from the external interface. assertion of the wr signal indicates that the zneo cpu is performing a write operation to the external memory or peripheral. cs0 /cs1 / cs2 cs3 /cs4 /cs5 o chip select outputs : these pins are the chip select output signals from the external interface. the cs output pins have programmable polarity through the external interface control register. bhen /blen o byte high enable and byte low enable indicators. wait i wait input : asserting this input signal will pause the cpu to provide slower external peripherals more time to complete bus transactions through the external interface. direct memory access controller dma0req dma1req dma2req i dma request inputs : each of the dma channels have an external request input which allows external peripherals to request access to the address and data buses for data transfer. dma0ack dma1ack dma2ack o dma request outputs : each of the dma channels have an acknowledge indicator output to notify external peripherals that their request for access to address and data buses has been approved. inter-integrated circuit controller scl i/o serial clock : this is an input or an output clock for the i 2 c. when the gpio pin is configured for alte rnate function to enable the scl function, this pin is open-drain. sda i/o serial data : this open-drain pin transfers data between the i 2 c and a slave. when the gpio pin is configured for alternate function to enable the sda function, this pin is open-drain. enhanced serial peripheral interface controller ss i/o slave select : this signal is an output or an input. if zneo is the spi master, this pin is configured as the slave select output. if zneo is the spi slave, this pin is an input slave select. sck i/o spi serial clock : the spi master supplies this pin. if the zneo Z16F series device is the spi mast er, this pin is an output. if the zneo Z16F series device is the spi slave, this pin is an input. mosi i/o master-out/slave-in : this signal is the data output from the spi master device and the data in put to the spi slave device. table 2. signal descriptions (continued) signal mnemonic i/o description www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 14 miso i/o master-in/slave-out : this pin is the data input to the spi master device and the data output from the spi slave device. uart controllers txd0/txd1 o transmit data : these signals transmit outputs from the uarts. rxd0/rxd1 i receive data : these signals receives inputs for the uarts and irdas. cts0 /cts1 i clear to send : these signals are control inputs for the uarts. de0/de1 o driver enable (de) : this signal allows automatic control of external rs-485 drivers. this signal is approximately the inverse of the transmit empty (txe) bit in the uart status 0 register. the de signal is used to ensure an external rs-485 driver is enabled when data is transmitted by the uart. general-purpose timers t0out/t0out t1out/t1out t2out/t2out o general-purpose timer outputs : these signals are output pins from the timers. t0in/t0in1/t0in2 /t1in/t2in i general-purpose timer inputs : these signals are used as the capture, gating, and counter inputs. pulse-width modulator for motor control pwmh0/pwmh1/ pwmh2 o pwm high output. pwml0/pwml1/ pwml2 o pwm low output. fault0/faulty i pwm fault condition input : fault0 and faulty are active low. analog ana[11:0] i analog input : these signals are inputs to the adc. vref i adc reference voltage input or internal reference output : the vref pin must be capacitively coupled to analog ground, if the internal voltage reference is selected as the adc reference voltage. a 10 mf capacitor is recommended. table 2. signal descriptions (continued) signal mnemonic i/o description caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 15 cinp i comparator positive input cinn i comparator negative input compout o comparator output opinp i operational amp lifier positive input opinn i operational amplifier negative input opout o operational amplifier output oscillators xin i external crystal input : this is the input pin to the crystal oscillator. a crystal is connected between it and the xout pin to form the oscillator. in addition, this pin is used with external rc networks or external clock drivers to provi de the system clock to the system. xout o external crystal output : this pin is the output of crystal oscillator. a crystal is connected between it and the xin pin to form the oscillator. this pin must be le ft unconnected when not using a crystal. on-chip debugger dbg i/o debug : this pin is the control and data input and output to and from the ocd. for operation of the ocd, all power pins (vdd and avdd) must be supplied with power and all ground pins (vss and avss) must be grounded. this pin is open-drain and must have an external pull-up resistor to ensure proper operation. reset reset i/o reset : bidirectional reset signals generates a reset when asserted (driven low) and drives a low output when the zneo is in reset. power supply vdd i power supply avdd i analog power supply vss i ground avss i analog ground table 2. signal descriptions (continued) signal mnemonic i/o description caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 16 pin characteristics table 3 provides information on the characteris tics of each pin available on the zneo products. data in table 3 is sorted alphabetically by the pin symbol mnemonic. table 3. pin characteristics of zneo symbol mnemonic direction reset direction active low/high tri?state output internal pull-up or pull-down schmitt trigger input open drain output avdd n/a n/a n/a n/a no no n/a avss n/a n/a n/a n/a no no n/a dbg i/o i n/a yes pull-up yes yes pa[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable pb[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable pc[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable pd[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable pe[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable pf[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable pg[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable ph[3:0] i/o i n/a yes pull-up, programmable yes yes, programmable pj[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable pk[7:0] i/o i n/a yes pull-up, programmable yes yes, programmable reset i/o i low n/a pull-up yes yes vref i/o i n/a yes n/a no no vdd n/a n/a n/a n/a no no n/a vss n/a n/a n/a n/a no no n/a www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 17 xin i i n/a n/a no no n/a xout o o n/a n/a no no no note: x represents integers 0, 1,... to indicate multiple pins with symbol mnemonics which differ only by an integer. table 3. pin characteristics of zneo (continued) symbol mnemonic direction reset direction active low/high tri?state output internal pull-up or pull-down schmitt trigger input open drain output www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y signal and pin descriptions zneo ? Z16F series product specification 18 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y address space zneo ? Z16F series product specification 19 address space the zneo cpu has a unique architecture with a single, unified 24-bit address space. it supports up to four memory areas: ? internal non-volatile memory (flash, eeprom, eprom, or rom). ? internal ram. ? internal i/o memory (internal peripherals). ? external memory (and/or me mory-mapped peripherals). the 24-bit address space supports up to 16 mb (16,777,216 bytes) of memory. the zneo cpu accesses any two of the abov e memory areas in parallel. in addition, the zneo cpu supports three different data widths: ? byte (8-bit) ? word (16-bit) ? quad (32-bit) the zneo cpu accesses memories of different bus width: ? 8-bit wide memories ? 16-bit wide memories memory map a memory map of the zn eo is illustrated in figure 6 on page 20. the location of internal non-volatile memory, internal ram, and in ternal i/o memory is illustrated in figure 6 on page 20. the external memory is placed at addresses which is not occupied by internal memory. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y address space zneo ? Z16F series product specification 20 figure 6. physical memory map to determine the amount of internal ram and internal non-volatile memory available for the specific device, see ordering information on page 360. internal non-volatile memory internal non-volatile memory co ntains executable program co de, constants, and data. for each product within the zneo cpu fam ily, a memory block beginning at address 00_0000h is reserved for user option bits and sy stem vectors (for example, reset, trap, interrupts, and system exceptions, etc.). table 4 on page 21 provides an example of reserved memory map for a zneo cpu product with 24 interrupt vectors. internal ram internal i/o memory internal non-volatile memory external memory ff_bfffh - top of internal ram 00_0000h - bottom of internal non-volatile memory ff_c000h ff_dfffh ff_e000h - bottom of i/o memory ff_ffffh - top of i/o memory external memory xx_xxxxh - bottom of internal ram xx_xxxxh - top of internal non-volatile memory (device specific) (device specific) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y address space zneo ? Z16F series product specification 21 internal ram internal ram is mainly empl oyed for data and stacks. ho wever, internal ram also contains program code for execution. most zneo cpu devices contain some internal ram. the top (highest address) of inte rnal ram is always located at address ff_bfffh . the bottom (lowest address) of internal ram is a function of the amount of internal ram available. to determine the amount of internal ram available, see ordering information on page 360 . input/output memory the zneo cpu supports 8 kb (8,192 bytes) of i/o memory space located at addresses ff_e000h through ff_ffffh . the i/o memory addresses are reserved for control of the zneo cpu, the on-chip peripherals, and th e i/o ports. refer to the device-specific product specification for descriptions of the pe ripheral and i/o control registers. attempts to read or execute from unavaila ble i/o memory addresses returns ffh . attempts to write to unavailable i/o memory addresses produce no effect. input/output memory precautions some control registers within the i/o memo ry provide read-only or write-only access. when accessing these read-only or write-only regi sters, ensure that the instructions do not attempt to read from a write-o nly register, or conversely write to a read-only register. cpu control registers some registers are reserved in 8 kb of i/ o memory for the zneo cpu control. these zneo cpu control registers are listed in table 5 on page 22. for detailed information on the operation of the zneo cpu control registers, refer to zneo cpu user manual (um0188), available for download at www.zilog.com . table 4. reserved memory map example memory address (hex) description 00_0000 - 00_0003 option bits 00_0004 - 00_0007 reset vector 00_0008 - 00_000b system exception vector 00_000c - 00_000f privileged trap vector 00_0010 - 00_006f interrupt vectors www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y address space zneo ? Z16F series product specification 22 external memory many zneo cpu products support external data and address buses for connecting to additional external memories and/or memory-m apped peripherals. the external addresses are used for storing program code, data, constant s, and stack, etc. attempts to read from or write to unavailable external addresses is undefined. endianness the zneo cpu accesses data in big endian order, that is, the address of a multi-byte word or quad points to the most significant byte. figure 7 displays the endianness of the zneo cpu. figure 7. endianness of words and quads table 5. zneo cpu control registers address (hex) register description register mnemonic ff_e004-ff_e007 program counter overflow pcov ff_e00c-ff_e00f stack pointer overflow spov ff_e010 flags flags ff_e012 cpu control cpuctl 00_0080h 00_0081h 00_0082h 00_0083h msb lsb address of quad 00_0080h 00_0081h msb lsb address of word www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y address space zneo ? Z16F series product specification 23 bus widths the zneo cpu accesses 8-bit or 16-bit memo ries. the data buses of the internal non-volatile memory and internal ram are 16-bit wide. the internal peripherals are a mix of 8-bit and 16-bit peripherals. the external me mory bus is configured as an 8-bit or 16-bit memory bus. if a word or quad operation occurs on a 16 -bit wide memory, the number of memory accesses depends on the alignment of the addr ess. if the address is aligned on an even boundary, a word operation takes one memo ry access and a quad operation takes two memory accesses. if the address is on an od d boundary (unaligned), a word operation takes two memory accesses and a quad operation takes three memory accesses. figure 8 displays the alignment word and qu ad operations on 16-bit memories. figure 8. alignment of word and quad operations on 16-bit memories lsb msb 000081h 000080h msb lsb 000083h 000080h aligned word access un aligned word access msb lsb 000081h 000080h 000083h 000082h msb lsb 000080h 000083h 000082h 000085h aligned quad access unaligned quad access 000081h 000082h 000084h 000081h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y address space zneo ? Z16F series product specification 24 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 25 peripheral address map table 6 provides the address map for th e peripheral space of the zneo ? Z16F series of products. not all devices and package styles in the zneo Z16F series support all peripherals or all gpio ports. registers fo r unimplemented peripherals are considered as reserved. table 6. register file address map address (hex) register description mnemonic reset (hex) page no zneo cpu base address = ff_e000 ff_e004-ff_e007 program counter overflow pcov 00ffffff refer to the zneo cpu user manual ff_e00c-ff_e00f stack pointer overflow spov 00000000 ff_e010 flags flags xx ff_e012 cpu control cpuctl 00 zneo trace address = ff_e014 ff_e013 trace control tracectl 00 325 ff_e014-ff_e017 trace address traceaddr xxxxxxxx 326 interrupt controller base address = ff_e020 ff_e020 system exception status high sysexcph 0000 85 ff_e021 system exception status low sysexcpl 0000 85 ff_e022 reserved ? xx ? ff_e023 last irq register lastirq 02 86 ff_e024-ff_e02f reserved ? ? ? ff_e030 interrupt re quest 0 irq0 00 86 ff_e031 interrupt reques t 0 set irq0set xx 86 ff_e032 irq0 enable high bit irq0enh 00 90 ff_e033 irq0 enable low bit irq0enl 00 90 ff_e034 interrupt re quest 1 irq1 00 88 ff_e035 interrupt request 1set irq1set xx 88 ff_e036 irq1 enable high bit irq1enh 00 92 ff_e037 irq1 enable low bit irq1enl 00 92 ff_e038 interrupt re quest 2 irq2 00 89 ff_e039 interrupt reques t 2 set irq2set xx 89 ff_e03a irq2 enable high bit irq2enh 00 93 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 26 ff_e03b irq2 enable low bit irq2enl 00 93 ff_e03c-ff_e03f reserved ? xx ? watchdog timer base address = ff_e040 ff_e040-ff_e041 reserved ? ? ? ff_e042 watchdog timer reload high byte wdth 04 242 ff_e043 watchdog timer reload low byte wdtl 00 242 ff_e044-ff_e04f reserved ? ? ? reset base address = ff_e050 ff_e050 reset status and control register rstscr xx 64 ff_e051-ff_e06f reserved ? xx ? flash controller base address = ff_e060 ff_e060 flash command register fcmd xx 263 ff_e060 flash status register fstat 00 263 ff_e061 flash control register fctl 00 264 ff_e062 flash sector protect register fsect 00 265 ff_e063 reserved ? xx ? ff_e064-ff_e065 flash page select register fpage 0000 265 ff_e066-ff_e067 flash frequency register ffreq 0000 266 external interface base address = ff_e070 ff_e070 external interface control extct 44 ff_e071 reserved ? ? ? ff_e072 chip select 0 control high extcs0h 44 ff_e073 chip select 0 control low extcs0l 45 ff_e074 chip select 1 control high extcs1h 44 ff_e075 chip select 1 control low extcs1l 46 ff_e076 chip select 2 control high extcs2h 44 ff_e077 chip select 2 control low extcs2l 47 ff_e078 chip select 3 control high extcs3h 44 ff_e079 chip select 3 control low extcs3l 47 ff_e07a chip select 4 control high extcs4h 44 ff_e07b chip select 4 control low extcs4l 47 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 27 ff_e07c chip select 5 control high extcs5h 44 ff_e07d chip select 5 control low extcs5l 47 ff_e07e-ff_e07f reserved ? ? ? on chip debugger = ff_e080 ff_e080 debug receive data dbgrxd xx 316 ff_e081 debug transmit data dbgtxd xx 316 ff_e082-ff_e083 debug baud rate dbgbr xxxx 317 ff_e084 debug line control dbglcr xx 317 ff_e085 debug status dbgstat xx 319 ff_e086 debug control dbgctl xx 320 hardware breakpoints = ff_e090 ff_e090-ff_e093 hardware breakpoint 0 hwbp0 00000000 324 ff_e094-ff_e097 hardware breakpoint 1 hwbp1 00000000 324 ff_e098-ff_e09b hardware breakpoint 2 hwbp2 00000000 324 ff_e09c-ff_e09f hardware breakpoint 3 hwbp3 00000000 324 oscillator control base address = ff_e0a0 ff_e0a0 oscillator control oscctl a0 333 ff_e0a1 oscillator divide oscdiv 00 334 gpio base address = ff_e100 gpio port a base address = ff_e100 ff_e100 port a input data pain xx 73 ff_e101 port a output data paout 00 73 ff_e102 port a data direction padd 00 74 ff_e103 port a high drive enable pahde 00 75 ff_e104 port a alternate function high paafh 00 75 ff_e105 port a alternate function low paafl 00 76 ff_e106 port a output control paoc 00 76 ff_e107 port a pull-up enable papue 00 77 ff_e108 port a stop mode recovery enable pasmre 00 77 ff_e109-ff_e10b port a reserved ? ? ? ff_e10c port a irq mux1 paimux1 00 78 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 28 ff_e10d port a reserved ? ? ? ff_e10e port a irq mux paimux 00 78 ff_e10f port a irq edge paiedge 00 79 gpio port b base address = ff_e110 ff_e110 port b input data pbin xx 73 ff_e111 port b output data pbout 00 73 ff_e112 port b data direction pbdd 00 74 ff_e113 port b high drive enable pbhde 00 75 ff_e114 reserved ? ? ? ff_e115 port b alternate function low pbafl 00 76 ff_e116 port b output control pboc 00 76 ff_e117 port b pull-up enable pbpue 00 77 ff_e118 port b stop mode recovery enable pbsmre 00 77 ff_e119-ff_e11f port b reserved ? ? ? gpio port c base address = ff_e120 ff_e120 port c input data pcin xx 73 ff_e121 port c output data pcout 00 73 ff_e122 port c data direction pcdd 00 74 ff_e123 port c high drive enable pchde 00 75 ff_e124 port c alternate function high pcafh 00 75 ff_e125 port c alternate function low pcafl 00 76 ff_e126 port c output control pcoc 00 76 ff_e127 port c pull-up enable pcpue 00 77 ff_e128 port c stop mode recovery enable pcsmre 00 77 ff_e129-ff_e12d port c reserved ? ? ? ff_e12e port c irq mux pcimux 00 79 ff_e12f port c reserved ? ? ? gpio port d base address = ff_e130 ff_e130 port d input data pdin xx 73 ff_e131 port d output data pdout 00 73 ff_e132 port d data direction pddd 00 74 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 29 ff_e133 port d high drive enable pdhde 00 75 ff_e134 port d alternate function high pdafh 00 75 ff_e135 port d alternate function low pdafl 00 76 ff_e136 port d output control pdoc 00 76 ff_e137 port d pull-up enable pdpue 00 77 ff_e138 port d stop mode recovery enable pdsmre 00 77 ff_e139-ff_e13f port d reserved ? ? ? gpio port e base address = ff_e140 ff_e140 port e input data pein xx 73 ff_e141 port e output data peout 00 73 ff_e142 port e data direction pedd 00 74 ff_e143 port e high drive enable pehde 00 75 ff_e144 reserved ? ? ? ff_e145 reserved ? ? ? ff_e146 port e output control peoc 00 76 ff_e147 port e pull-up enable pepue 00 77 ff_e148 port e stop mode re covery enable pesmre 00 77 ff_e149-ff_e14f port e reserved ? ? ? gpio port f base address = ff_e150 ff_e150 port f input data pfin xx 73 ff_e151 port f output data pfout 00 73 ff_e152 port f data direction pfdd 00 74 ff_e153 port f high drive enable pfhde 00 75 ff_e154 reserved ? ? ? ff_e155 port f alternate function low pfafl 00 76 ff_e156 port f output control pfoc 00 76 ff_e157 port f pull-up enable pfpue 00 77 ff_e158 port f stop mode recovery enable pfsmre 00 77 ff_e159-ff_e15f port f reserved ? ? ? gpio port g base address = ff_e160 ff_e160 port g input data pgin xx 73 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 30 ff_e161 port g output data pgout 00 73 ff_e162 port g data direction pgdd 00 74 ff_e163 port g high drive enable pghde 00 75 ff_e164 reserved ? ? ? ff_e165 port g alternate function low pgafl 00 76 ff_e166 port g output control pgoc 00 76 ff_e167 port g pull-up enable pgpue 00 77 ff_e168 port g stop mode recovery enable pgsmre 00 77 ff_e169-ff_e16f port g reserved ? ? ? gpio port h base address = ff_e170 ff_e170 port h input data phin xx 73 ff_e171 port h output data phout 00 73 ff_e172 port h data direction phdd 00 74 ff_e173 port h high drive enable phhde 00 75 ff_e174 port h alternate function high phafh 00 75 ff_e175 port h alternate function low phafl 00 76 ff_e176 port h output control phoc 00 76 ff_e177 port h pull-up enable phpue 00 77 ff_e178 port h stop mode recovery enable phsmre 00 77 ff_e179-ff_e17f port h reserved ? ? ? gpio port j base address = ff_e180 ff_e180 port j input data pjin xx 73 ff_e181 port j output data pjout 00 73 ff_e182 port j data direction pjdd 00 74 ff_e183 port j high drive enable pjhde 00 75 ff_e184 reserved ? ? ? ff_e185 reserved ? ? ? ff_e186 port j output control pjoc 00 76 ff_e187 port j pull-up enable pjpue 00 77 ff_e188 port j stop mode recovery enable pjsmre 00 77 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 31 ff_e189-ff_e18f port j reserved ? ? ? gpio port k base address = ff_e190 ff_e190 port k input data pkin xx 73 ff_e191 port k output data pkout 00 73 ff_e192 port k data direction pkdd 00 74 ff_e193 port k high drive enable pkhde 00 75 ff_e194 reserved ? ? ? ff_e195 port k alternate function low pkafl 00 76 ff_e196 port k output control pkoc 00 76 ff_e197 port k pull-up enable pkpue 00 77 ff_e198 port k stop mode recovery enable pksmre 00 77 ff_e199-ff_e19f port k reserved ? ? ? serial channels base address = ff_e200 lin-uart 0 base address = ff_e200 ff_e200 lin-uart0 transmit data u0txd xx 153 lin-uart0 receive data u0rxd xx 153 ff_e201 lin-uart0 status 0 u0stat0 0000011xb 154 ff_e202 lin-uart0 control 0 u0ctl0 00 159 ff_e203 lin-uart0 control 1 u0ctl1 00 162 ff_e204 lin-uart0 mode select and status u0mdstat 00 160 ff_e205 lin-uart0 address compare register u0addr 00 164 ff_e206 lin-uart0 baud rate high byte u0brh ff 164 ff_e207 lin-uart0 baud rate low byte u0brl ff 165 ff_e208-ff_e20f reserved ? xx ? lin-uart 1 base address = ff_e210 ff_e210 lin-uart1 transmit data u1txd xx 153 lin-uart1 receive data u1rxd xx 153 ff_e211 lin-uart1 status 0 u1stat0 0000011xb 154 ff_e212 lin-uart1 control 0 u1ctl0 00 159 ff_e213 lin-uart1 control 1 u1ctl1 00 162 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 32 ff_e214 lin-uart1 mode select and status u1mdstat 00 160 ff_e215 lin-uart1 address compare register u1addr 00 164 ff_e216 lin-uart1 baud rate high byte u1brh ff 164 ff_e217 lin-uart1 baud rate low byte u1brl ff 165 ff_e218-ff_e23f reserved ? xx ? i 2 c base address = ff_e240 ff_e240 i 2 c data i2cdata 00 227 ff_e241 i 2 c interrupt status i2cistat 80 227 ff_e242 i 2 c control i2cctl 00 229 ff_e243 i 2 c baud rate high byte i2cbrh ff 230 ff_e244 i 2 c baud rate low byte i2cbrl ff 231 ff_e245 i 2 c state i2cstate c0 231 ff_e246 i 2 c mode i2cmode 00 234 ff_e247 i 2 c slave address i2cslvad 00 236 ff_e248-ff_e25f reserved ? xx ? enhanced serial peripheral interface base address = ff_e260 ff_e260 espi data espidata xx 192 ff_e261 reserved ? xx ff_e262 espi control espictl 00 193 ff_e263 espi mode espimode 00 195 ff_e264 espi status espistat 01 197 ff_e265 espi state espistate 00 198 ff_e266 espi baud rate hi gh byte espibrh ff 200 ff_e267 espi baud rate low byte espibrl ff 201 timers - base address = fff_e300 timer 0 (general-purpose timer) base address = ff_e300 ff_e300 timer 0 high byte t0h 00 106 ff_e301 timer 0 low byte t0l 01 107 ff_e302 timer 0 reload high byte t0rh ff 107 ff_e303 timer 0 reload low byte t0rl ff 107 ff_e304 timer 0 pwm high byte t0pwmh 00 108 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 33 ff_e305 timer 0 pwm low byte t0pwml 00 108 ff_e306 timer 0 control 0 t0ctl0 00 109 ff_e307 timer 0 control 1 t0ctl1 00 110 timer 1 (general-purpose timer) base address = ff_e310 ff_e310 timer 1 high byte t1h 00 106 ff_e311 timer 1 low byte t1l 01 107 ff_e312 timer 1 reload high byte t1rh ff 107 ff_e313 timer 1 reload low byte t1rl ff 107 ff_e314 timer 1 pwm high byte t1pwmh 00 108 ff_e315 timer 1 pwm low byte t1pwml 00 108 ff_e316 timer 1 control 0 t1ctl0 00 109 ff_e317 timer 1 control 1 t1ctl1 00 110 timer 2 (general-purpose timer) base address = ff_e320 ff_e320 timer 2 high byte t2h 00 106 ff_e321 timer 2 low byte t2l 01 107 ff_e322 timer 2 reload high byte t2rh ff 107 ff_e323 timer 2 reload low byte t2rl ff 107 ff_e324 timer 2 pwm high byte t2pwmh 00 108 ff_e325 timer 2 pwm low byte t2pwml 00 108 ff_e326 timer 2 control 0 t2ctl0 00 109 ff_e327 timer 2 control 1 t2ctl1 00 110 pulse width modulator (pwm) base address = ff_e380 ff_e380 pwm control 0 pwmctl0 00 124 ff_e381 pwm control 1 pwmctl1 00 126 ff_e382 pwm deadband pwmdb 00 127 ff_e383 pwm minimum pulse width filter pwmmpf 00 127 ff_e384 pwm fault mask pwmfm 00 128 ff_e385 pwm fault status pwmfstat 00 129 ff_e386 pwm input sample register pwmin 00 131 ff_e387 pwm output control pwmout 00 132 ff_e388 pwm fault control pwmfctl 00 130 ff_e389 reserved ? ? ? table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 34 ff_e38a current-sense sample and hold control 0 csshr0 00 133 ff_e38b current-sense sample and hold control 1 csshr1 00 133 ff_e38c-ff_e38b reserved ? ? ? ff_e38c pwm high byte pwmh xx 122 ff_e38d pwm low byte pwml xx 122 ff_e38e pwm reload high byte pwmrh ff 123 ff_e38f pwm reload low byte pwmrl ff 123 ff_e390 pwm 0 high side duty cycle high byte pwmh0dh 00 124 ff_e391 pwm 0 high side duty cycle low byte pwmh0dl 00 124 ff_e392 pwm 0 low side duty cycle high byte pwml0dh 00 124 ff_e393 pwm 0 low side duty cycle low byte pwml0dl 00 124 ff_e394 pwm 1 high side duty cycle high byte pwmh1dh 00 124 ff_e395 pwm 1 high side duty cycle low byte pwmh1dl 00 124 ff_e396 pwm 1 low side duty cycle high byte pwml1dh 00 124 ff_e397 pwm 1 low side duty cycle low byte pwml1dl 00 124 ff_e398 pwm 2 high side duty cycle high byte pwmh2dh 00 124 ff_e399 pwm 2 high side duty cycle low byte pwmh2dl 00 124 ff_e39a pwm 2 low side duty cycle high byte pwml2dh 00 124 ff_e39b pwm 2 low side duty cycle low byte pwml2dl 00 124 ff_e39c-ff_e3bf reserved for pwm ? ? ? dma block base address = ff_e400 dma request selection control table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 35 ff_e400 dma0 request select dma0reqsel 00 281 ff_e401 dma1 request select dma1reqsel 00 281 ff_e402 dma2 request select dma2reqsel 00 281 ff_e403 dma3 request select dma3reqsel 00 281 ff_e404-f reserved ? ? ? dma channel 0 base address = ff_e410 ff_e410 dma0 control0 dma0ctl0 00 285 ff_e411 dma0 control1 dma0ctl1 00 285 ff_e412 dma0 transfer length high dma0txlnh 00 287 ff_e413 dma0 transfer length low dma0txlnl 00 287 ff_e414 reserved ? ? ? ff_e415 dma0 destination ad dress upper dma0daru 00 287 ff_e416 dma0 destination address high dma0darh 00 288 ff_e417 dma0 destination address low dma0darl 00 288 ff_e418 reserved ? ? ? ff_e419 dma0 source addr ess upper dma0saru 00 288 ff_e41a dma0 source addr ess high dma0sarh 00 289 ff_e41b dma0 source ad dress low dma0sarl 00 289 ff_e41c reserved ? ? ? ff_e41d dma0 list address upper dma0laru 00 289 ff_e41e dma0 list address high dma0larh 00 290 ff_e41f dma0 list address low dma0larl 00 290 dma channel 1 base address = ff_e420 ff_e420 dma1 control0 dma1ctl0 00 285 ff_e421 dma1 control1 dma1ctl1 00 285 ff_e422 dma1 transfer length high dma1txlnh 00 287 ff_e423 dma1 transfer length low dma1txlnl 00 287 ff_e424 reserved ? ? ? ff_e425 dma1 destination ad dress upper dma1daru 00 287 ff_e426 dma1 destination address high dma1darh 00 288 ff_e427 dma1 destination address low dma1darl 00 288 ff_e428 reserved ? ? ? table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 36 ff_e429 dma1 source addr ess upper dma1saru 00 288 ff_e42a dma1 source addr ess high dma1sarh 00 289 ff_e42b dma1 source ad dress low dma1sarl 00 289 ff_e42c reserved ? ? ? ff_e42d dma1 list address upper dma1laru 00 289 ff_e42e dma1 list address high dma1larh 00 290 ff_e42f dma1 list address low dma1larl 00 290 dma channel 2 base address = ff_e430 ff_e430 dma2 control0 dma2ctl0 00 285 ff_e431 dma2 control1 dma2ctl1 00 285 ff_e432 dma2 transfer length high dma2txlnh 00 287 ff_e433 dma2 transfer length low dma2txlnl 00 287 ff_e434 reserved ? ? ? ff_e435 dma2 destination ad dress upper dma2daru 00 287 ff_e436 dma2 destination address high dma2darh 00 288 ff_e437 dma2 destination address low dma2darl 00 288 ff_e438 reserved ? ? ? ff_e439 dma2 source addr ess upper dma2saru 00 288 ff_e43a dma2 source addr ess high dma2sarh 00 289 ff_e43b dma2 source ad dress low dma2sarl 00 289 ff_e43c reserved ff_e43d dma2 list address upper dma2laru 00 289 ff_e43e dma2 list address high dma2larh 00 290 ff_e43f dma2 list address low dma2larl 00 290 dma channel 3 base address = ff_e440 ff_e440 dma3 control0 dma3ctl0 00 285 ff_e441 dma3 control1 dma3ctl1 00 285 ff_e442 dma3 transfer length high dma3txlnh 00 287 ff_e443 dma3 transfer length low dma3txlnl 00 287 ff_e444 reserved ? ? ? ff_e445 dma3 destination ad dress upper dma3daru 00 287 ff_e446 dma3 destination address high dma3darh 00 288 ff_e447 dma3 destination address low dma3darl 00 288 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 37 ff_e448 reserved ? ? ? ff_e449 dma3 source addr ess upper dma3saru 00 288 ff_e44a dma3 source addr ess high dma3sarh 00 289 ff_e44b dma3 source ad dress low dma3sarl 00 289 ff_e44c reserved ? ? ? ff_e44d dma3 list address upper dma3laru 00 289 ff_e44e dma3 list address high dma3larh 00 290 ff_e44f dma3 list address low dma3larl 00 290 analog block base address = ff_e500 adc base address = ff_e500 ff_e500 adc0 control register adc0ctl 00 247 ff_e501 reserved ? ? ? ff_e502 adc0 data high byte register adc0d_h xx 248 ff_e503 adc0 data low bits register adc0d_l xx 249 ff_e504 adc sample and settling time register adcsst 0f 249 ff_e505 adc sample hold time adcst 3f 250 ff_e506 adc clock prescale register adccp 00 251 ff_e507 adc0 max register adc0max 00 252 ff_e508-ff_e50f reserved ? ? ? ff_e510 comparator and op-amp control cmpopc 00 255 ff_e511 reserved ? ? ? ff_e512 adc sample timer capture high adctcaph xx 252 ff_e513 adc sample timer capture low adctcapl xx 253 option trim registers base address = ff_ff00 ff_ff00-ff_ff24 reserved for internal zilog ? use ? ? ? ff_ff25 ipo trim 1 ipotrim1 xx 297 ff_ff26 ipo trim 2 ipotrim2 xx 297 ff_ff27 adc reference voltage trim adctrim xx 298 note: xx=undefined. table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page no www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y peripheral address map zneo ? Z16F series product specification 38 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 39 external interface the external interface allows seamless connectio n to external memory and/or peripherals. the configurable nature of the external inte rface supports connectio n with many different bus styles and signal formats. bit-wise cont rol of the address, data, and control signals means no wasted gpio pins. other featur es of the external interface includes: ? hardware bus controller with programma ble signal polarity for chip selects. ? programmable wait state generator. ? selectable address and data bus widths. ? six external chip selects. ? isa-compatible mode. ? external program execution and stack operations. ? external wa i t pin for slow peripherals. external interface signals table 7 lists the external interface signals. the external interface consists of a 24-bit address bus, an 8-bit/16-bit bidirectional data bus, and control signals (read, write, chip selects, and wait). it is not necessary to use a ll pins for proper operation of the external interface. the external interface signals are enabled pin-by-pin using the gpio alternate functions. for more information on gpio alternate functions, see general-purpose input/ output on page 68. table 7. external interface signals description external interface signal direction data[7:0] input / output data[15:8] input / output addr[7:0] output addr[15:8] output addr[23:16] output wr output rd output cs0 output wait input www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 40 chip selects the chip selects support connec tion of multiple memories an d peripherals to the external interface. figure 9 on page 40 displays the memory map of the chip selects. the chip select boundaries are at fixed addresses. on -chip memory always have priority over external memory. chip select 0 has the lowest priority and chip select 5 has the highest priority. cs1 output cs2 output cs3 output cs4 output cs5 output figure 9. chip select boundary addr essing with 128 kb internal flash table 7. external interface signals description (continued) external interface signal direction 16 mb memory 000000h ffffffh addresses 128 kb 020000h cs0 cs1 800000h 7fffffh cs5 cs4 cs3 cs3 - cs5 01ffffh internal flash f00000h efffffh ffc800h ffd000h ffcfffh ffd800h ffd7ffh ffdfffh addresses zoom in on cs3 - cs5 cs2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 41 tools compatibility guidelines the external interface offers the designer the fl exibility to place extern al devices in almost any range of the 24-bit address space. the prim ary hardware consideration is that more chip selects are available in high memory a nd devices needing more than 15 wait states must use one of chip selects cs[2?5]. once a design is completed, it is necessary to develop software for it. the ta sk of designing application so ftware is much easier if the hardware designer consider s the following guidelines: ? the microcontroller?s internal flash must be enabled during software development. this simplifies downloading of program co de and allows the zds ii default program configuration to be used. if the internal fl ash is disabled, the address space beginning at 00_0000h must address external flash or other memory containing the necessary option bits, vectors, and application startup code. table 8. example usage of chip selects chip select memory/peripheral lower address upper address typical uses 64 kb internal flash 000000h 00ffffh program code, look-up tables, and interrupt vectors. cs0 8 mb external rom or flash 010000h 7fffffh program code and look-up tables. lowest 64 kb of the 8 mb is inaccessible as the on-chip flash has higher priority for addresses 000000h through 00ffffh . cs1 128 kb external ram 080000h 09ffffh stack and data is placed anywhere in cs1 address space except where higher priority cs2 or cs3 overlaps. 0affffh 0effffh unused addresses as no external memory placed in these locations. cs2 external ethernet mac f00000h f3ffffh ethernet mac is an example of an external communication peripheral that is connected to the external interface. cs3 external can controller. ffc800h ffcfffh can controller is another example of an external communication peripheral that is connected to the external interface. f80000h ffffffh unused addresses as no external memory or peripherals placed in these locations. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 42 ? any external non-volatile memory must be located above the internal flash in the address space, but below any vo latile (random access) memory. there is a gap or hole in the address space between internal and external non-volatile memory, and between non-volatile and volatile memory. ? any external volatile (random access) me mory must be located at or above 80_0000h in the 24-bit address space (in the cs1 rang e). this is a requirement of the zds ii gui. volatile memory on cs0 is located in a lower address range if it is configured by adding an edited linker range command to the additional linker commands field of the zds ii project settings. ? external volatile memory falling below ff_8000h must be addressed as a contiguous block. the zds ii c-compiler large model do es not support holes in 32-bit addressed volatile memory. there is a hole between this memory and volatile memory at or above ff_8000h , however. ? external volatile memory at or above ff_8000h must be addressed as a block contiguous with the microc ontroller?s internal ram. the zds ii c-compiler small model does not support holes in 16 -bit addressable volatile memory. ? external volatile memory must not be loca ted above internal ram, which ends at ff_bfffh . this is a requirement of the zds ii gui. volatile memory is located at ff_c000h and extend up to ff_dfffh if the space is not used for i/o, but the range must be configured by adding an edite d linker range comma nd to the additional linker commands field of the project se ttings. the debugger me mory window always displays this range as part of the i/o data space, however. ? the zds ii gui assumes external i/o is located in the range ff_c000h to ff_dfffh . any external i/o that is located elsewher e is accessed using absolute addressing. the debugger memory window displays all addresses below ff_c000h as part of the memory space. for details on how the zds ii develo pment tools use memory, refer to zilog developer studio ii? zneo user manual ( um0171) . external wait pin operation setup of the external wait pin is selected by the gpio a lternate function. when using the external wait pin, at least one internal wait state must be added to allow sufficient address valid to wait input setup time. operation wait state generator programmable wait states are inserted to prov ide external devices with additional clock cycles to complete their r ead and write operations. the number of wait states are www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 43 controlled by the csxwait[3:0] field and the prxwait[1:0] field as shown in the chip select control registers on page 44. the wait states idle the zneo cpu for the specified number of system clock cycles. a maximum of 31 waits states are inserted. an example of wait state operation is illustrated in figure 10 . in this example, the external interface has been configured to provide two wait st ates. see the detailed timing diagrams in external interface timing on page 48. isa-compatible mode configuring the external interface for isa mode adjusts the read timing to follow the isa mode commonly employed in pc and related applications. in isa mode, assertion of the read signal (rd ) is delayed one-half system clock. also, an extra wait state is added during read operations. figure 10. external interface wait state operation example (write operation) xin addr[23:0] data[15:0] cs tclk (output) wr twait 2 wait states enabled in wait twait state generator www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 44 external interface contr ol register definitions the following section describes the various control registers. external interface control register the external interface control register enables the interface an d sets the internal memory size (see table 9 ). bussel ? bus select external interface enable 00 = no external bus. 01 = 8-bit external bus in terface is enabled (port e). 1x = 16-bit external bus interface is enabled (port j and port e). memsize ? select internal memory size 00 = 128 kb of internal memory. 01 = 64 kb of internal memory. 10 = 32 kb of internal memory. 11 = no internal memory. chip select c ontrol registers the chip select control registers control the ch ip select outputs. each chip select has a high byte and low byte. table 9. external interface control register (extct) bits 7 6 5 4 3 2 1 0 field bussel memsize reserved reset 00 00 0000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_e070h table 10. external chip select control registers high (extcsxh) bits 7 6 5 4 3 2 1 0 field csxen polsel csxisa w/b reserved reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_(e072, e074, e076, e078, e07a, e07c)h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 45 reserved ?these bits are reserved and must be programmed to zero. csen?chip select enable 0 = csx is disabled 1 = csx is enabled polsex?polarity select 0 = csx is active low 1 = csx is active high cs x isa?chip select isa mode enable 0 = isa mode disabled 1 = isa mode enabled w/b?word or byte mode select per chip select for 16-bit or 8-bit peripherals 0 = external interface uses data[15:0] for this chip select 1 = external interface uses data[7:0] for this chip select table 11 lists the external chip select control registers low for cs0 (extcs0l). this register sets the number of wait states for ch ip select 0. waits are only added if the chip select is enabled. chip select 0 is enabled automatically in romless mode. pr0wait[2:0]?post read wait selection 00 = 0 wait state 01 = 1 wait state 10 = 2 wait states 11 = 3 wait states cs0wait?chip select 0 wait selection 0000 = 0 wait state 0001 = 1 wait state 0010 = 2 wait states 0011 = 3 wait states 0100 = 4 wait states 0101 = 5 wait states 0110 = 6 wait states table 11. external chip select control registers low for cs0 (extcs0l) bits 7 6 5 4 3 2 1 0 field reserved pr0wait cs0wait reset 00111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_(e073)h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 46 0111 = 7 wait states 1000 = 8 wait states 1001 = 9 wait states 1010 = 10 wait states 1011 = 11 wait states 1100 = 12 wait states 1101 = 13 wait states 1110 = 14 wait states 1111 = 15 wait states table 12 shows the external chip select control regi sters low for cs1(extsc1l). this register sets the number of wait states for ch ip select 1. waits are only added if the chip select is enabled. pr1wait[2:0]?post read wait selection 00 = 0 wait state 01 = 1 wait state 10 = 2 wait states 11 = 3 wait states cs1wait?chip select 1 wait selection 0000 = 0 wait state 0001 = 1 wait state 0010 = 2 wait states 0011 = 3 wait states 0100 = 4 wait states 0101 = 5 wait states 0110 = 6 wait states 0111 = 7 wait states 1000 = 8 wait states 1001 = 9 wait states 1010 = 10 wait states 1011 = 11 wait states 1100 = 12 wait states table 12. external chip select control registers low for cs1 (extcs1l) bits 7 6 5 4 3 2 1 0 field reserved pr1wait cs1wait reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_(e075)h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 47 1101 = 13 wait states 1110 = 14 wait states 1111 = 15 wait states table 13 lists the external chip select control re gisters low for cs2 to cs5 (extcsxl). this register sets the number of wait states for chip selects 2 through 5. waits are only added if the chip select is enabled. pr x wait[2:0]?post read wait selection 00 = 0 wait state 01 = 1 wait state 10 = 2 wait states 11 = 3 wait states csxwait?chip select x wait selection 0000 = 0 wait state 0001 = 2 wait state 0010 = 4 wait states 0011 = 6 wait states 0100 = 8 wait states 0101 = 10 wait states 0110 = 12 wait states 0111 = 14 wait states 1000 = 16 wait states 1001 = 18 wait states 1010 = 20 wait states 1011 = 22 wait states 1100 = 24 wait states 1101 = 26 wait states 1110 = 28 wait states 1111 = 30 wait states table 13. external chip select control registers low for cs2 to cs5 (extcsxl) bits 7 6 5 4 3 2 1 0 field reserved prxwait csxwait reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_(e077, e079, e07b, e07d)h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 48 external interface timing the following sections describe the external interface timing. external interface wr ite timing - normal mode figure 11 on page 49 and table 14 provide timing information for the external interface performing a write operation. in figure 11 on page 49, it is assumed that the wait state generator is configured to provide 1 wait st ate during write operations. the external wa i t input pin is generating an additional wait period. also in figure 11 on page 49, it is assumed that the chip select (cs ) signal has been configured for active low operation. though the internal system clock is not provid ed as an external signal, it provides a useful reference for control signal events. note th at at the completion of a write cycle, the de-assertion of the wr signal is fed back from the pin and used on chip to control the de-assertion of the data, cs , address and byte enable signals to assure proper timing of the data hold. table 14. external interface timing for a write operation - normal mode parameter abbreviation delay (ns) minimum maximum t 1 sys clk rise to address valid delay 10 t 2 wr rise to address output hold time 3 t 3 sys clk rise to data valid delay 10 t 4 wr rise to data output hold time 3 t 5 sys clk rise to cs assertion delay 10 t 6 wr rise to cs deassertion hold time 3 t 7 sys clk rise to wr assertion delay 1/2 tc l k + 1 0 t 8 sys clk rise to wr deassertion hold time 3 t 9 wait input pin assertion to xin rise setup time 1 t 10 wait input pin deassertion to xin rise setup time 1 t 11 sys clk rise to dmaack assertion delay 10 t 12 sys clk rise to dmaack deassertion hold time 3 t 13 sys clk rise to bhen or blen assertion delay 10 t 14 wr rise to bhen or blen deassertion hold time 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 49 figure 11. external interface timing for a write operation - normal mode xin addr[23:0] data[15:0] cs t clk wr t wait 1 wait state from wait state generator and 1 wait state from external wait pin t wait t 1 t 3 t 5 t 7 t 8 t 6 t 4 t 2 wait t 9 t 10 (from pin) dmaack t 11 t 12 bhen / blen t 13 t 14 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 50 external interface wr ite timing - isa mode figure 12 on page 51 and table 15 provide timing information for the external interface performing a write operation. in figure 12 on page 51, it is assumed that the wait state generator has been configured to provid e 1 wait state during write operations. the external wait input pin is generating an additiona l wait period. as with the normal mode, the wr signal is fed back from the pin and used on chip to time the removal of the data signals to ensure proper timing of the data hold. table 15. external interface timing for a write operation - isa mode parameter abbreviation delay (ns) minimum maximum t 1 xin rise to address valid delay 10 t 2 xin rise to address output hold time 3 t 3 xin rise to data valid delay 10 t 4 wr rise to data output hold time 3 t 5 xin rise to cs assertion delay 10 t 6 xin rise to cs deassertion hold time 3 t 7 xin fall to wr assertion delay 10 t 8 xin fall to wr deassertion hold time 3 t 9 wait input pin assertion to xin rise setup time 1 t 10 wait input pin deassertion to xin rise setup time 1 t 11 xin rise to dmaack assertion delay 10 t 12 xin rise to dmaack deassertion hold time 3 t 13 xin rise to bhen or blen assertion delay 10 t 14 xin rise to bhen or blen deassertion hold time 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 51 figure 12. external interface timing for a write operation - isa mode xin addr[23:0] data[15:0] cs t clk wr t wait 1 wait state from wait state generator and 1 wait state from external wait pin t wait t 1 t 3 t 5 t 7 t 8 t 6 t 4 t 2 wait t 9 t 10 (from pin) dmaack t 12 t 11 bhen / blen t 14 t 13 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 52 external interface read timing - normal mode figure 13 on page 53 and table 16 provide timing information for the external interface performing a read operation in normal mode. in figure 13 on page 53, it is assumed the wait state generator has been configur ed to provide 2 wait states during read operations. for proper data hold time determina tion, you must know th at the input data is captured on chip during the rising edge of the system clock prior to the rd signal de-assertion. the read signal (rd ) timing is shown for bo th normal and isa modes. table 16. external interface timing for a read operation - normal mode parameter abbreviation delay (ns) minimum maximum t 1 xin rise to address valid delay 10 t 2 xin rise to address output hold time 3 t 3 data input valid to xin rise setup time 3 t 4 rd rise to data input hold time 0 t 5 xin rise to cs assertion delay 10 t 6 xin rise to cs deassertion hold time 3 t 7 xin rise to rd assertion delay 10 t 8 xin rise to rd deassertion hold time 3 t 9 wait input pin assertion to xin rise setup time 1 t 10 wait input pin deassertion to xin rise setup time 1 t 11 xin rise to dmaack assertion delay 10 t 12 xin rise to dmaack deassertion hold time 3 t 13 xin rise to bhen or blen assertion delay 10 t 14 xin rise to bhen or blen deassertion hold time 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 53 figure 13. external interface timing for a read operation - normal mode xin addr[23:0] data[15:0] cs t clk rd t wait 1 wait state from wait state generator and 1 wait state from external wait pin t wait t 1 t 3 t 5 t 7 t 4 t 2 wait t 9 t 10 (from pin) dmaack t 11 bhen / blen t 13 t 12 t 14 t 8 t 6 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 54 figure 14 and table 16 provide timing information for the external interface performing a read operation in normal mode with a post read wait state. the configuration is the same as in figure 13 , with the exception of the post read wait state. figure 14. external interface timing for a read operation - 2 wait states and 1 post read wait state xin addr[23:0] data[15:0] cs t clk rd t wait 1 wait state from wait state generator and 1 wait state from external wait pin t wait t 1 t 3 t 5 t 7 t 4 t 2 wait t 9 t 10 (from pin) t 8 t 6 t prwait 1 post read wait state www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 55 external interface r ead timing - isa mode figure 15 on page 56 and table 17 provide timing information for the external interface performing a read opera tion in isa mode. in figure 15 on page 56, it is assumed the wait state generator has been configured to prov ide 2 wait states duri ng read operations. in figure 15 on page 56, it is also assumed that the chip select (cs ) signals have been configured for active low oper ation. the read signal (rd ) timing is shown for both normal and isa modes. table 17. external interface timing for a read operation - isa mode parameter abbreviation delay (ns) minimum maximum t 1 xin rise to address valid delay 10 t 2 xin rise to address output hold time 3 t 3 data input valid to xin rise setup time 3 t 4 xin rise to data input hold time 3 t 5 xin rise to cs assertion delay 10 t 6 xin rise to cs deassertion hold time 3 t 7 xin fall to rd assertion delay 10 t 8 xin fall to rd deassertion hold time 3 t 9 wait input pin assertion to xin rise setup time 1 t 10 wait input pin deassertion to xin rise setup time 1 t 11 xin rise to dmaack assertion delay 10 t 12 xin rise to dmaack deassertion hold time 3 t 13 xin rise to bhen or blen assertion delay 10 t 14 xin rise to bhen or blen deassertion hold time 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 56 figure 15. external interface timing for a read operation - isa mode xin addr[23:0] data[15:0] cs t clk rd t wait 1 wait state from wait state generator and 1 wait state from external wait pin t wait t 1 t 3 t 5 t 7 t 8 t 6 t 4 t 2 wait t 9 t 10 (from pin) dmaack t 12 t 11 bhen / blen t 14 t 13 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y external interface zneo ? Z16F series product specification 57 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y reset and stop mode recovery zneo ? Z16F series product specification 58 reset and stop mode recovery the reset controller within the zneo ? Z16F series controls reset and stop mode recovery operation. in a typical operation, the following events causes a reset to occur: ? power-on reset. ? voltage brownout. ? wdt time-out (when configured through the wdt_res option bit to initiate a reset). ? external reset pin assertion. ? ocd initiated reset ( ocdctl[0] set to 1). ? fault detect logic. when zneo Z16F series is in stop mode, a stop mode recovery is initiated by either of the following: ? wdt time-out. ? gpio port input pin transition on an enabled stop mode recovery source. reset types the zneo Z16F series provides two different types of reset operation (system reset and stop mode recovery). the type of reset is a function of both the current operating mode of the zneo Z16F series device and the source of the reset. table 18 lists the types of reset and their operating characteristics. table 18. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency peripheral control registers zneo cpu reset latency (delay) system reset reset (as applicable) reset a minimum of 66 internal precision oscillator cycles. stop mode recovery unaffected, except rstsrc and oscctl registers reset a minimum of 66 internal precision oscillator cycles. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y reset and stop mode recovery zneo ? Z16F series product specification 59 system reset during a system reset, the zneo Z16F series devi ce is held in reset for 66 cycles of the ipo. at the beginning of reset, all gpio pins are configured as inputs. all gpio programmable pull-ups are disabled. at the start of a system reset, the moto r control pwm outputs are forced to high- impedance momentarily. when th e option bits that control the off-state have been properly evaluated, the pwm outputs are for ced to the progra mmed off-state. during reset, the zneo cpu and on-chip peri pherals are non-active; however, the ipo and wdt oscillator continue to run. during th e first 50 clock cycles, the internal option bit registers are initialized, after which the system clock for the core and peripherals begins operating. the zneo cpu and on-chi p peripherals remain non-active through the next 16 cycles of the system clock, after wh ich the internal reset signal is deasserted. on reset, control registers within the register file that have a defined reset value are loaded with their reset values. other control registers (including the flags) and general- purpose ram are undefined following reset. th e zneo cpu fetches the reset vector at program memory address 0004h and loads that value into the program counter. program execution begins at the reset vector address. table 19 lists the system reset sources as a func tion of the operating mode. the following text provides more detailed information on the individual reset sources. note that a por/vbo event always has priority over all ot her possible reset sources to ensure that a full system reset occurs. table 19. system reset sources and resulting reset action operating mode system reset source action normal or halt modes por/vbo system reset wdt time-out when configured for reset system reset reset pin assertion system reset write rstscr[0] to 1 system reset fault detect logic reset system reset stop mode por/vbo system reset reset pin assertion system reset fault detect logic reset system reset www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y reset and stop mode recovery zneo ? Z16F series product specification 60 power-on reset each device in the zneo Z16F series contains an internal por circuit. the por circuit monitors the supply voltage and holds the device in the reset state until the supply voltage reaches a safe operating level. after the supp ly voltage exceeds the por voltage threshold (v por ) and has stabilized, the por counter is enable d and counts 50 cycles of the ipo. at this point, the system clock is enabled and the por counter counts a total of 16 system clock pulses. the device is held in the r eset state until the second por counter sequence has timed out. after the zneo Z16F series exits the por state, the zneo cpu fetches the reset vector. following por, the por status bit in the reset status and control register on page 64 is set to 1. figure 15 displays power-on reset operatio n. for the por threshold voltage (v por ), see table 74 on page 343. figure 15. power-on reset operation voltage brownout reset the zneo Z16F series provides low volta ge brownout (vbo) protection. the vbo circuit senses the supply voltage when it dr ops to an unsafe level (below the vbo threshold voltage) and forces the device into the reset state. while the supply voltage v cc = 0.0 v v cc = 3.3 v v por v vbo internal precision oscillator internal reset signal program execution oscillator start-up system clock system clock option bit counter delay counter delay not to scale www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y reset and stop mode recovery zneo ? Z16F series product specification 61 remains below the por voltage threshold (v por ), the vbo holds the device in the reset state. when the supply vo ltage exceeds the v por and is stabilized, the device progresses through a full system reset sequen ce, as described in the section power-on reset on page 60. following power-on reset, the por status bit in the reset source register is set to 1. figure 16 displays voltage brownout operation. for vbo and por threshold voltages (v vbo and v por ), see stop mode current versus v dd on page 343. the vbo circuit is either enabled or disabled during stop mode. operation during stop mode is controlled by the vbo_ao option bit. for inform ation on configuring vbo_ao, see option bits on page 293. figure 16. voltage brownout reset operation watchdog timer reset if the device is in normal or halt mode, the wdt initiates a system reset at time- out if the wdt_res option bit is set to 1. this setting is the default (unprogrammed) setting of the wdt_res option bit. the wdt status bit in the reset status and control register on page 64 is set to signify that th e reset was initiated by the wdt. v cc = 3.3 v v por v vbo internal reset signal program execution program execution voltage brownout v cc = 3.3 v internal precision oscillator system clock system clock option bit counter delay counter delay www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y reset and stop mode recovery zneo ? Z16F series product specification 62 external pin reset the input-only r eset pin has a schmitt-triggered input, an internal pu ll-up, an analog filter and a digital filter to reject noise. once the reset pin is asserted for at least four system clock cycles, the devi ce progresses through the system reset sequence. while the reset input pin is asserted low, the zneo Z16F series device continues to be held in the reset state. if the reset pin is held low beyond the system reset time-out, the device exits the reset state 16 sy stem clock cycles following reset pin deassertion. if the reset pin is released before the sy stem reset time-out, the reset pin is driven low by the chip until the completion of the time -out as described in the next section. in stop mode, the digital filter is bypas sed as the system clock is disabled. following a system reset initiated by the external reset pin, the ext status bit in the reset status and control register on page 64 is set to 1. external reset indicator during system reset, the reset pin functions as an open drain (active low) reset mode indicator in add ition to the input functionality. this reset output feature allows a zneo Z16F series device to reset other compon ents to which it is connected, even if the reset is caused by internal sources such as por, vbo, or wdt events and as an indication of when the reset sequence completes. once an internal reset event occurs, the internal circu itry begins driving the reset pin low. the reset pin is held low by the internal circuitry until the appropriate delay listed in table 18 on page 58 has elapsed. user reset a system reset is initiated by setting rstscr[ 0]. if the write was caused by the ocd, the ocd is not reset. fault detect logic reset fault detect circuitry exists to detect illegal state changes which is caused by transient power or electrostatic discharge events. when such a fault is detected, a system reset is forced. following the system reset, the fltd bit in the reset status and control register on page 64 is set. stop mode recovery stop mode is entered by execution of a stop instruction by the zneo cpu. for detailed information on stop mode, see low-power modes on page 66. during stop mode recovery, the device is held in reset for 66 cycles of the internal precision oscillator. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y reset and stop mode recovery zneo ? Z16F series product specification 63 stop mode recovery only affects the contents of the reset status and control register on page 64 and oscillator control register on page 333. stop mode recovery does not affect any other values in the register file, includin g the stack pointer, register pointer, flags, peripheral control registers, and general-purpose ram. the zneo cpu fetches the reset vector at program memory addresses 0004h-0007h and loads that value into th e program counter. program execution begins at the reset vector address. following stop mode recovery, the stop bit in the reset status and control register on page 64 is set to 1. table 20 lists the stop mode recovery sources and resulting actions. the following text provides more detailed in formation on each of the stop mode recovery sources. stop mode recovery using wdt time-out if the wdt times out during stop mode, the device undergoes a stop mode recovery sequence. in the reset status and control register on page 64, the wdt and stop bits are set to 1. if the wdt is configured to genera te a system exception on time-out, the zneo cpu services the wdt system exception fo llowing the normal stop mode recovery sequence. stop mode recovery using a gpio port pin transition each of the gpio port pins is configured as a stop mode recovery input source. if any gpio pin enabled as a stop mode recovery so urce, a change in th e input pin value (from high to low or from low to high) initiat es stop mode recovery. the gpio stop mode recovery signals are filtered to reject pulses less than 10 ns (typical) in duration. in the reset status and control register on page 64, the stop bit is set to 1. short pulses on th e port pin initiates stop mode recovery without initiat - ing an interrupt (if enabled for that pin). table 20. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode wdt time-out when configured for reset stop mode recovery wdt time-out when configured for system exception stop mode recovery followed by wdt system exception data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y reset and stop mode recovery zneo ? Z16F series product specification 64 reset status and control register the reset status and control (rstscr) register (see table 21 ) records the cause of the most recent reset or stop mode recovery. a ll status bits are updated on each reset or stop mode recovery event. table 22 indicate the possible states of the reset status bits following a reset or stop mode recovery event. the user_rst bit in this register allows software controlled reset of the part pin. this is a write only bit that causes a system reset with the result identified by the usr bit after being executed. 0 = no action. 1 = causes system reset. table 22. reset status register values following reset table 21. reset status and control register (rstscr) bits 7 6 5 4 3 2 1 0 field por stop wdt ext flt usr reserved user_rst reset see table 22 below r/w rr r rrr r w addr ff-e050h reset or stop mode recovery event por stop wdt ext flt usr power-on reset 1 0 0 0 0 0 reset using reset pin assertion 0 0 0 1 0 0 reset using wdt time-out 0 0 1 0 0 0 reset from fault detect logic 0 0 0 0 1 0 stop mode recovery using gpio pin transition 0 1 0 0 0 0 stop mode recovery using wdt time-out 0 1 1 0 0 0 reset using software control - write 1 to bit 0 of this register 000001 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y reset and stop mode recovery zneo ? Z16F series product specification 65 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y low-power modes zneo ? Z16F series product specification 66 low-power modes the zneo ? Z16F series products contain advan ced integrated power-saving features. power management functions are divided into three categories to include cpu operating modes, peripheral power control, and programmable option bits. the highest level of power reduction is provided throug h a combination of all functions. stop mode execution of the zneo cpu?s stop instruction places the device into stop mode. in stop mode, the operating characteristics are: ? ipo is stopped; xin and xout pins are driven to v ss . ? system clock is stopped. ? zneo cpu is stopped. ? program counter (pc) stops incrementing. ? if enabled for operation duri ng stop mode, the wdt and its internal rc oscillator continue to operate. ? if enabled for operation in stop mode th rough the associated option bit, the vbo protection circuit continues to operate. ? all other on-chip peripherals are non-active. to minimize current in stop mode, all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v dd or v ss ), the vbo protection must be disabled, and wdt must be disabled. the device is brought out of stop mode using stop mode recovery. for detailed information on stop mode recovery, see reset and stop mode recovery on page 58. to prevent excess current consumption when using an external clock source in stop mode, the external cl ock must be disabled. halt mode execution of the zneo cpu?s halt instruction places the device into halt mode. the following are the operating characteris tics in halt mode: ? system clock is enabled and continues to operate. ? zneo cpu is stopped. ? pc stops incrementing. caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y low-power modes zneo ? Z16F series product specification 67 ? wdt?s internal rc oscillator continues to operate. ? if enabled, the wdt continues to operate. ? all other on-chip peripherals continue to operate. the zneo cpu is brought out of halt mode by any of the following operations: ? interrupt or system exception. ? wdt time-out (system exception or reset). ? power-on reset. ? vbo reset. ? external reset pin assertion. ? instantaneous halt mode recovery. to minimize current in halt mode, all gpio pi ns which are configured as inputs must be driven to one of the supply rails (v dd or v ss ). peripheral-level power control on-chip peripherals in zneo Z16F series pa rts automatically enter a low power mode after reset and whenever the peripheral is disabled. to minimize power consumption, unused peripherals must be disabled. see the individual peripheral chapters for specific register settings to enable or disable the peripheral. power control option bits user programmable option bits are available in some versions of the zneo Z16F series devices that enable very low power stop mode operation. these options include disabling the vbo protection circuits and disabling the wdt oscillator. for detailed description of the user options that affect power management, see option bits on page 293. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 68 general-purpose input/output the zneo ? Z16F series products contain general-purpose input/output (gpio) pins arranged as ports a?k. each port contains control and data registers. the gpio control registers are used to determine data direction, open-drain, output drive current, and alternate pin functions. each port pin is individually programmable. gpio port availability by device table 23 lists the port pins available by device and package pin count. architecture figure 17 displays a simplified block diagram of a gpio port pin. figure 17 does not displays the ability to accomm odate alternate functions and variable port current drive strength. table 23. gpio port availability by device device pin-count port a port b port c port d port e port f port g port h port j port k Z16F2811 100-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] [7:0] [7:0] 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] - - Z16F6411 100-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] [7:0] [7:0] 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] - - Z16F3211 100-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] [7:0] [7:0] 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] - Z16F2810 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] - - 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] - - 64-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] - - www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 69 gpio alternate functions many gpio port pins are used for gpio and to provide access to the on-chip peripheral functions such as timers, serial communicatio n devices, and external data and address bus. the port a?k alternate function registers configure these pins for either gpio or alternate function operation. when a pin is configured for alternate function, control of the port pin direction (i/o) is passed from the port a?k data direction registers to the alternate function assigned to this pin. table 24 on page 70 lists the alternate functions associated with each port pin. for detailed information on enabling th e external interface data signals, see external interface on page 39. when the external interface da ta signals are enabled for an 8-bit port, the other gpio functionality including a lternate functions cannot be used. figure 17. gpio port pin block diagram d q dq gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt trigger vdd pull-up enable www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 70 table 24. port alternate function mapping port pin alternate function 1 alternate function 2 alternate function 3 external interface port a pa0 t0in / t0out dma0req t0inpb pa1 t0out dma0ack pa2 de0 faulty pa3 cts0 fault0 pa4 rxd0 cs1 pa5 txd0 cs2 pa6 scl cs3 pa7 sda cs4 port b pb0/t0in0 ana0 pb1/t0in1 ana1 pb2/t0in2 ana2 pb3 ana3/opout pb4 ana4 pb5 ana5 pb6 ana6/opinp/cinn pb7 ana7/opinn port c pc0 t1in / t1out dma1req cinn pc1 t1out dma1ack compout pc2 ss cs4 pc3 sck dma2req pc4 mosi dma2ack pc5 miso cs5 pc6 t2in / t2out pwmh0 pc7 t2out pwml0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 71 port d pd0 pwmh1 addr[20] pd1 pwml1 addr[21] pd2 pwmh2 addr[22] pd3 de1 addr[16] pd4 rxd1 addr[18] pd5 txd1 addr[19] pd6 cts1 addr[17] pd7 pwml2 addr[23] port e pe0 data[0] pe1 data[1] pe2 data[2] pe3 data[3] pe4 data[4] pe5 data[5] pe6 data[6] pe7 data[7] port f pf0 addr[0] pf1 addr[1] pf2 addr[2] pf3 addr[3] pf4 addr[4] pf5 addr[5] pf6 addr[6] pf7 addr[7] table 24. port alternate function mapping (continued) port pin alternate function 1 alternate function 2 alternate function 3 external interface www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 72 port g pg0 addr[8] pg1 addr[9] pg2 addr[10] pg3 addr[11] pg4 addr[12] pg5 addr[13] pg6 addr[14] pg7 addr[15] port h ph0 ana8 wr ph1 ana9 rd ph2 ana10 cs0 ph3 ana11/cpinp wait port j pj0 data[8] pj1 data[9] pj2 data[10] pj3 data[11] pj4 data[12] pj5 data[13] pj6 data[14] pj7 data[15] port k pk0 bhen pk1 blen pk2 cs0 pk3 cs1 pk4 cs2 pk5 cs3 pk6 cs4 pk7 cs5 table 24. port alternate function mapping (continued) port pin alternate function 1 alternate function 2 alternate function 3 external interface www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 73 gpio interrupts many of the gpio port pins are used as interrupt sources. some port pins are configured to generate an interrupt request on either the ri sing edge or falling edge of the pin input signal. other port pin interrupts generate an inter rupt when any edge occurs (both rising and falling). for more information on interrupts using the gpio pins, see interrupt controller on page 80. gpio control register definitions port a-k input data registers reading from the port a-k input data registers (see table 25 ) returns the sampled values from the corresponding port pins. the port a-k input data registers are read-only. pin[7:0]?port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). port a-k output data registers the port a-k output data registers (see table 26 ) write output data to the pins. table 25. port a-k input data registers (pxin) bits 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr addr ff_e100, ff_e110, ff_e120, ff_e130, ff_e140, ff_e150, ff_e160, ff_e170, ff_e180, ff_e190 table 26. port a-k output data registers (p x out) bits 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e101, ff_e111, ff_e121, ff_e131, ff_e141, ff_e151, ff_e161, ff_e171, ff_e181, ff_e191 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 74 pout[7:0]?port output data these bits contain the data to be driven out from the port pins. the values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1= drive a logical 1 (high). high value is not dr iven if the drain has been disabled by setting the corresponding port output control register bit to 1. port a-k data direction registers the port a-k data direction registers (see table 27 ) configure the specified port pins as either inputs or outputs. dd[7:0]?data direction these bits control the direction of the associat ed port pin. port alternate function operation overrides the data direction register setting. 0 = output data in the port a-k output data register is driven onto the port pin. 1 = input the port pin is sampled and the value written into the port a-k input data register. the output driver is high impedance. table 27. port a-k data direction registers (p x dd) bits 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e102, ff_e112, ff_e122, ff_e132, ff_e 142, ff_e152, ff_e162, ff_e172, ff_e182, ff_e192 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 75 port a-k high drive enable registers setting the bits in the port a-k high drive enable registers (see table 28 ) to 1, configures the specified port pins for high current output drive operation. the port a-k high drive enable registers affect the pins directly, and as a result, alternate functions are also affected. phde[7:0]?port high drive enabled 0 = the port pin is configured for standard output current drive. 1 = the port pin is configured for high output current drive. port a-k alternate function high and low registers the port a-k alternate function high and low registers (see table 29 and table 30 on page 75) select the alternate functions for th e selected pins. to determine the alternate function associated with each port pin, see gpio alternate functions on page 69. when changing alternate functions, it is recommended to use word data mode instructions to perform simultaneous writes to the port alternate function high and low registers. do not enable alternate function for gpio port pins which do not have an associated alternate functio n. failure to follow this guideline will result in undefined operation. table 28. port a-k high drive enable registers (p x hde) bits 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e103, ff_e113, ff_e123, ff_e133, ff_e 143, ff_e153, ff_e163, ff_e173, ff_e183, ff_e193 table 29. port a-k alternate function high registers (pxafh) bits 7 6 5 4 3 2 1 0 field afh[7] afh[6] afh[5] afh[4] afh[3] afh[2] afh[1] afh[0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e104, ff_e124, ff_e134, ff_e174 caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 76 table 30. port a-k alternate function low registers (p x afl) port a-k output control registers setting the bits in the port a-k output control registers (see table 32 ) to 1 configures the specified port pins for open-drain operation. thes e registers affect the pins directly and as a result, alternate functions are also affected. enabling the i 2 c controller automatically configures the scl and sda pins as open-drain; independent of the setting in the output control registers that have the scl and sda alternate functions. poc[7:0]?port output control these bits function independently of the alternate function bits and disable the drains if set to 1. bits 7 6 5 4 3 2 1 0 field afl[7] afl[6] afl[5] afl[4] afl[3] afl[2] afl[1] afl[0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e105, ff_e115, ff_e125, ff_e135, ff_e155, ff_e165, ff_e175, ff_e195 table 31. alternate function enabling afh[ x ] afl[ x ]priority 0 0 no alternate function enabled 0 1 alternate function 1 enabled 1 0 alternate function 2 enabled 1 1 alternate function 3 enabled note : x indicates the register bits from 0 through 7. table 32. port a-k output control registers (p x oc) bits 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e106, ff_e116, ff_e126, ff_e136, ff_e 146, ff_e156, ff_e166, ff_e176, ff_e186, ff_e196 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 77 0 = the drains are enabled for any output mode. 1 = the drain of the associated pin is disabled (open-drain mode). port a-k pull-up enable registers setting the bits in the port a-k pull-up enable registers (see table 33 ) to 1, enables a weak internal resistive pull-up on the specified port pins. these registers affect the pins directly and as a result, alternate functions are also affected. pue[7:0]?port pull-up enable these bits function independently of the alternat e function bit and enable the weak pull-up if set to 1. 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. port a-k stop mode recover y source enable registers setting the bits in the port a-k stop mode recovery source enable registers (see table 34 ) to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enable d as a stop mode re covery source initiates stop mode recovery. table 33. port a-k pull-up enable registers (p x pue) bits 7 6 5 4 3 2 1 0 field pue7 pue6 pue5 pue4 pue3 pue2 pue1 pue0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e107, ff_e117, ff_e127, ff_e137, ff_e147, ff_e157, ff_e167, ff_e177, ff_e187, ff_e197 table 34. port a-k stop mode recovery source enable registers (p x smre) bits 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e108, ff_e118, ff_e128, ff_e138, ff_e148, ff_e158, ff_e168, ff_e178, ff_e188, ff_e198 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 78 psmre[7:0]?port stop mode recovery source enabled 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin during stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mode recovery source. any logic transition on this pin during stop mode initiates stop mode recovery. port a irq mux1 register the port irq mux1 register (see table 35 ) selects either port a/d pins or the comparator/ dbg channel as interrupt sources. cpimux?comparator interrupt mux 0 = select port a7/d7 based upon the port a irq edge register as the interrupt source. 1 = select the comparator as the interrupt source. dbgimux?debug interrupt mux 0 = select port a0/d0 based on the port a irq edge register as the interrupt source. 1 = select the dbg as the interrupt source. port a irq mux register the port irq mux register (see table 36 ) selects either port a or port d pins as interrupt sources. table 35. port a irq mux1 register (paimux1) bits 7 6 5 4 3 2 1 0 field cpimux reserved dbgimux reset 00000000 r/w r/wr/wrrrrrr/w addr ff_e10c table 36. port a irq mux register (paimux) bits 7 6 5 4 3 2 1 0 field paimux7 paimux6 paimux5 paimux4 paimux3 paimux2 paimux1 paimux0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e10e www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y general-purpose input/output zneo ? Z16F series product specification 79 paimux[7:0]?port a/d interrupt source 0 = select port a x as interrupt source. 1 = select port d x as interrupt source. port a irq edge register the port irq edge register (see table 37 ) selects either positive or negative edge as the port pin interrupt sources. paiedge[7:0]?port a/d interrupt edge 0 = select port a/d pin negedge as interrupt source. 1 = select port a/d pins posedge as interrupt source. port c irq mux register the port c irq mux register (see table 38 ) selects either port c pins or the dma channels as interrupt sources. reserved ?these bits are reserved. pcimux[3:0]?port c interrupt mux 0 = select dma chan[3:0] as interrupt source. 1 = select port c pins as interrupt source. table 37. port a irq edge register (paiedge) bits 7 6 5 4 3 2 1 0 field paiedge 7 paiedge 6 paiedge 5 paiedge 4 paiedge 3 paiedge 2 paiedge 1 paiedge 0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e10f table 38. port c irq mux register (pcimux) bits 7 6 5 4 3 2 1 0 field reserved pcimux3 pcimux2 pcimux1 pcimux0 reset 00000000 r/w rrrrr/wr/wr/wr/w addr ff_e12e www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 80 interrupt controller the interrupt controller on the zneo ? Z16F series products pr ioritize interrupt requests from on-chip peripherals and the gpio port pi ns. the features of the interrupt controller includes: ? flexible gpio interrupts: ? eight selectable rising and falling edge gpio interrupts ? four dual-edge interrupts ? three levels of individually programmable interrupt priority ? software interrupt re quests (irq) assertion the irqs allow peripheral devices to suspen d cpu operation in an orderly manner and force the cpu to start an isr. usually this se rvice routine is involv ed with exchange of data, status information, or control information between the cpu and the interrupting peripheral. when the service routine is comp leted, the cpu returns to the operation from which it was interrupted. system exceptions are non-maskable requests which allow critical system functions to suspend cpu operation in an orderly manner an d force the cpu to start a service routine. usually this service routine tries to determ ine how critical the exception is. when the service routine is complete, the cpu retu rns to the operation from which it was interrupted. the zneo Z16F series supports both vectored and polled interrupt handling. for polled interrupts, the interrupt control has no effe ct on operation. for more information on interrupt servicing by the zneo cpu, refer to the zneo cpu user manual available for download at www.zilog.com . www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 81 interrupt vector listing table 39 lists all the interrupts available in order of priority. table 39. interrupt vectors in order of priority priority program memory vector address programmable priority? interrupt source highest 0004h no reset (not an interrupt) 0008h no system exceptions 000ch no reserved 0010h yes timer 2 0014h yes timer 1 0018h yes timer 0 001ch yes uart 0 receiver 0020h yes uart 0 transmitter 0024h yes i 2 c 0028h yes spi 002ch yes adc0 0030h yes port a7 or port d7, rising or falling input edge or comparator output rising and falling edge (source selected in porta irq mux registers) 0034h yes port a6 or port d6, rising or falling input edge 0038h yes port a5 or port d5, rising or falling input edge 003ch yes port a4 or port d4, rising or falling input edge 0040h yes port a3 or port d3, rising or falling input edge 0044h yes port a2 or port d2, rising or falling input edge 0048h yes port a1 or port d1, rising or falling input edge 004ch yes port a0 or port d0, ri sing or falling input edge or ocd interrupt (source selected in porta irq mux registers) 0050h yes pwm timer 0054h yes uart 1 receiver 0058h yes uart 1 transmitter 005ch yes pwm fault www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 82 the most significant byte (msb) of the four byte interrupt vector is not used. the vector is stored in the three least significant byte (lsb) of the vector (see table 40 ). 0060h yes port c3, both input edges/dma 3 0064h yes port c2, both input edges/dma 2 0068h yes port c1, both input edges/dma 1 lowest 006ch yes port c0, both input edges/dma 0 table 40. interrupt vector placement vector byte data 0 reserved 1 irq vector[23:16] 2 irq vector[15:8] 3 irq vector[7:0] table 39. interrupt vectors in order of priority (continued) priority program memory vector address programmable priority? interrupt source www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 83 architecture figure 18 displays a block diagram of the interrupt controller. figure 18. interrupt controller block diagram operation master interrupt enable the master interrupt enable bit in the flag re gister globally enables or disables interrupts. this bit has been moved to the flag register (bit-0). thus, anytime the register is loaded, it changes the state of th e irqe bit. for the iret instruction the bit is set based on what has been pushed on the stack. interrupts are globally enabled by any of the following actions: ? execution of an en able interrupt ( ei ) instruction ? writing 1 to the irqe bit in the flag register interrupts are globally disabled by any of the following actions: ? execution of a disable interrupt ( di ) instruction ? zneo cpu acknowledgement of an interru pt service request from the interrupt controller ? writing 0 to the irqe bit in the flag register vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 84 ? reset ? execution of a trap instruction ? all system exceptions interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest priority , and level 1 is the lowest priority. if all the interrupts are enabled with identical interrupt priority (for example, all interrupts enabled as level 2 interrupts), the interrupt priority is assigned from highest to lowest as specified in table 39 on page 81. level 3 interrupts always have higher priority than level 2 interrupts, which in turn, always have higher priority than level 1 interrupts. within each interrupt priority levels (level 1, level 2, or level 3), priority is assigned as specified in table 39 . reset and system exceptions have the highest priority. system exceptions system exceptions are genera ted for stack overflow, illegal instructions, divide-by-zero, and divide overflow, etc. the system exceptions are not affected by the irqe and share a single vector. each exception has a bit in the system exception status regist er. when a system exception occurs it pushes the program counter and the flags on the stack, fetches the system exception vector from 000008h (similar to a irq) and the bit ass ociated with that exception is set in the status register. ad ditional exceptions from the same source are blocked until the status bit of the particular ex ception is cleared by wr iting 1 to that status bit. other types of exceptions occur while se rvicing an exception. wh en this happens the processor again vectors to the system except ion vector and sets the associated exception status bit. the service routine would then have to respond to the new exception. for illegal instructions the progra m counter and flags is only push ed on the stack once. if the associated exception bit is not reset, the program counter and flags will not get pushed again. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (single pulse). when the interrupt request is acknowledged by the zneo cpu, the corresponding bit in the interrupt request regist er is cleared until the next interrupt occurs. writing 1 to the corresponding bit in the inte rrupt request register clears the interrupt request. program code generates interrupts directly. writing a 1 to the appropriate bit in the interrupt request set register triggers an in terrupt (assuming that interrupts are enabled). when the interrupt request is acknowledged by the zneo cp u, the bit in the interrupt request register is auto matically cleared to 0. note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 85 system exception status registers when a system exception occurs the system exception status registers is read to determine which system exception occurred. these registers are read individually or read as a 16-bit quantity. spovf ? stack pointer overflow if this bit is 1, a stack pointer overflow excep tion occurred. writing 1 to this bit clears it to 0. pcovf?program counter overflow if this bit is 1, a program coun ter overflow exception occurred. writing 1 to this bit clears it to 0. div0?divide by zero if this bit is 1, a divide operation was exec uted where the denominator was zero. writing 1 to this bit clear it to 0. divovf?divide over flow if this bit is 1, a divide overflow occurred. a divide overflow happens when the result is greater than ffffffffh. writing 1 to this bit clears it to 0. ill?illegal instruction if this bit is 1, an illegal instruction occurred. writing 1 to this bit clears it to 0. table 41. system exception register high (sysexcph) bits 7 6 5 4 3 2 1 0 field spovf pcovf div0 divovf ill reserved reset 00000000 r/w r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c addr ff_e020h table 42. system exception register low (sysexcpl) bits 7 6 5 4 3 2 1 0 field reserved wdtosc priosc wdt reset 00000000 r/w r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c addr ff_e021h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 86 reserved ?these bits are reserved wdtosc?wdt oscillator fail if this bit is 1, a wdt oscillator fail exceptio n occurred. writing 1 to this bit clears it to 0. priosc?primary oscillator fail if this bit is 1, a primary oscillator fail exceptio n occurred. writing 1 to this bit clears it to 0. wdt?watchdog timer interrupt if this bit is 1, a wdt exception occurred. writing 1 to this bit clears it to 0. last irq register when an interrupt occurs, the 5th bit value of th e interrupt vector is stored in the register. this register allows the softwa re to determine which interrupt source was last serviced. it is used by rtos which have a single in terrupt entry point. to implement this the software must set all interrupt vectors to the entry point address. the entry point service routine then reads this register to determine which sour ce caused the interrupt or exception and respond accordingly. interrupt request 0 register the interrupt request 0 (irq0) register (see table 44 on page 87) stores the interrupt requests for both vectored and polled interru pts. when a request is presented to the interrupt controller, the corresponding bit in the irq0 register becomes 1. if interrupts are globally enabled (vectored inte rrupts), the interrupt controller passes an interrupt request to the zneo cpu. if interrupts are globally disabled (polled interrupts), the zneo cpu reads the interrupt request 0 register to de termine if any interrupt requests are pending. writing 1 to the bits in this register clears the interrupt. the bits of this register are set by writing 1 to the interrupt request 0 se t regsiter (irq0set) at address ff_e031h. table 43. last irq register (lastirq) bits 7 6 5 4 3 2 1 0 field always 0 irqadr always 00 reset 00000100 r/w r r/w r/w r/w r/w r/w r r addr ff_e023h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 87 t2i?timer 2 interrupt request 0 = no interrupt request is pending for timer 2. 1 = an interrupt request from timer 2 is awaiting ser vice. writing 1 to this bit resets it to 0. t1i?timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. writing 1 to this bit resets it to 0. t0i?timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting ser vice. writing 1 to this bit resets it to 0. u0rxi?uart 0 receiver interrupt request 0 = no interrupt request is pe nding for the uart 0 receiver. 1 = an interrupt request from the uart 0 receiver is awaiting service. writing 1 to this bit resets it to 0. u0txi?uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. 1 = an interrupt request from the uart 0 transm itter is awaiting service. writing 1 to this bit resets it to 0. table 44. interrupt request 0 register (irq0) and interrupt request 0 set register (irq0set) bits 7 6 5 4 3 2 1 0 field t2i t1i t0i u0rxi u0txi i2ci spii adci reset 00000000 r/w r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c addr ff_e030h field t2i t1i t0i u0rxi u0txi i2ci spii adci reset 00000000 r/w wwwwwwww addr ff_e031h note: irq0set at address ff_e031h is write only and used to set the interrupts identified. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 88 i2ci?i2c interrupt request 0 = no interrupt request is pending for the i2c. 1 = an interrupt request from the i2c is awaitin g service. writing 1 to this bit resets it to 0. spii?spi interrupt request 0 = no interrupt request is pending for the spi. 1 = an interrupt request from th e spi is awaiting service. writin g 1 to this bit resets it to 0. adci?adc interrupt request 0 = no interrupt request is pending for adc. 1 = an interrupt request from adc is awaiting service. writing 1 to this bit resets it to 0. interrupt request 1 register the interrupt request 1 (irq1) register (see table 45 ) stores interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq1 register be comes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controlle r passes an interrupt request to the zneo cpu. if interrupts are globally disabled ( polled interrupts), the zneo cpu reads the interrupt request 1 register to determine, if any interrupt requests are pending. writing 1 to the bits in this register clears the interrupt. th e bits of this register are set by writing 1 to the interrupt request 1 set regsite r (irq1set) at address ff_e035h. table 45. interrupt request1 register (irq1) and interrupt request1 set register (irq1set) pad x i?port a/d pin x interrupt request 0 = no interrupt request is pending for gpio port a/d pin x . 1 = an interrupt request from gpio port a/d pin x is awaiting service. writing 1 to these bits resets it to 0. bits 7 6 5 4 3 2 1 0 field pad7i pad6i pad5i pad4i pad3i pad2i pad1i pad0i reset 00000000 r/w r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c addr ff_e034h field pad7i pad6i pad5i pad4i pad3i pad2i pad1i pad0i reset 00000000 r/w wwwwwwww addr ff_e035h note : irq1set at address ff_e035h is write onl y and used to set the interrupts identified. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 89 here x indicates the specific gpio port pin number (0 through 7). pad7i and pad0i have interrupt sources other than port a and port d as selected by the port a irq mux registers. pad7i is configured to provide the comparator interrupt. pad0i is configured to provide the ocd interrupt. these bits are set any time the selected port is toggled. the setting of these bits are not affected by the associated interrupt enable bits. interrupt request 2 register the interrupt request 2 (irq2) register (see table 46 ) stores interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq2 register be comes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controlle r passes an interrupt request to the zneo cpu. if interrupts are globally disabled ( polled interrupts), the zneo cpu reads the interrupt request 1 register to determine, if any interrupt requests are pending. writing 1 to the bits in this register clears the interrupt. th e bits of this register are set by writing 1 to the interrupt request 2 set regsite r (irq2set) at address ff_e039h. pwmti?pwm timer interrupt request 0 = no interrupt request is pending for the pwm timer. 1 = an interrupt request from the pwm timer is awaiting service. wr iting 1 to this bit resets it to 0. table 46. interrupt request 2 register (irq2) and interrupt request 2 set register (irq2set) bits 7 6 5 4 3 2 1 0 field pwmti u1rxi u1txi pwmfi pc3i/ dma3i pc2i/ dma2i pc1i/ dma1i pc0i/ dma0i reset 00000000 r/w r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c addr ff_e038h field pwmti u1rxi u1txi pwmfi pc3i/ dma3i pc2i/ dma2i pc1i/ dma1i pc0i/ dma0i reset 00000000 r/w wwwwwwww addr ff_e039h note : irq2set at address ff_e039h is write onl y and used to set the interrupts identified. note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 90 u1rxi?uart 1 receiver interrupt request 0 = no interrupt request is pe nding for the uart 1 receiver. 1 = an interrupt request from the uart 1 receive r is awaiting service. writing 1 to this bit resets it to 0. u1txi?uart 1 transmitter interrupt request 0 = no interrupt request is pending for the uart 1 transmitter. 1 = an interrupt request from the uart 1 transm itter is awaiting servic e. writing 1 to this bit resets it to 0. pwmfi? pwm fault interrupt request 0 = no interrupt request is pending for the pwm fault. 1 = an interrupt request from the pwm fault is awa iting service. writing 1 to this bit resets it to 0. pc x i/dmaxi?port c pin x or dma x interrupt request 0 = no interrupt request is pending for gpio port c pin x or dma x. 1 = an interrupt request from gpio port c pin x or dmax is awaiting service. writing 1 to this bit resets it to 0. where x indicates the specific gpio port c pin or dma number (0 through 3). irq0 enable high a nd low bit registers the irq0 enable high and low bit registers (see table 48 and table 49 ) form a priority encoded enabling for interrupts in the interrupt request 0 register. priority is generated by setting bits in each register. table 47 describes the priority control for irq0. table 47. irq0 enable and priority encoding irq0enh[ x ]irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high note: x indicates the register bits from 0 through 7. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 91 t2enh ? timer 2 interrupt request enable high bit t1enh ? timer 0 interrupt request enable high bit t0enh ? timer 0 interrupt request enable high bit u0renh ? uart 0 receive interrupt request enable high bit u0tenh ? uart 0 transmit interru pt request enable high bit i2cenh ? i2c interrupt re quest enable high bit spienh ? spi interrupt request enable high bit adcenh ? adc interrupt re quest enable high bit t2enl?timer 2 interrupt request enable low bit t1enl?timer 1 interrupt request enable low bit t0enl?timer 0 interrupt request enable low bit u0renl?uart 0 receive interru pt request enable low bit u0tenl?uart 0 transmit interrupt request enable low bit i2cenl? i2c interrupt re quest enable low bit spienl? spi interrupt request enable low bit adcenl?adc interrupt request enable low bit table 48. irq0 enable high bit register (irq0enh) bits 7 6 5 4 3 2 1 0 field t2enh t1enh t0enh u0renh u0tenh i2cenh spienh adcenh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e032h table 49. irq0 enable low bit register (irq0enl) bits 7 6 5 4 3 2 1 0 field t2enl t1enl t0enl u0renl u0tenl i2cenl spienl adcenl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e033h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 92 irq1 enable high a nd low bit registers the irq1 enable high and low bit registers (see table 51 and table 52 ) form a priority encoded enabling for interrupts in the interrupt request 1 register. priority is generated by setting bits in each register. table 50 describes the priority control for irq1. pad x enh?port a/d bit[ x ] interrupt request enable high bit . pa x enl?port a/d bit[ x ] interrupt request enable low bit. table 50. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 01level 1low 1 0 level 2 nominal 1 1 level 3 high note: x indicates the register bits from 0 through 7. table 51. irq1 enable high bit register (irq1enh) bits 7 6 5 4 3 2 1 0 field pad7enh pad6enh pad5enh pad4enh pad3enh pad2enh pad1enh pad0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e036h table 52. irq1 enable low bit register (irq1enl) bits 7 6 5 4 3 2 1 0 field pad7enl pad6enl pad5enl pad4enl pad3enl pad2enl pad1enl pad0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e037h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 93 irq2 enable high a nd low bit registers the irq2 enable high and low bit registers (see table 54 and table 55 ) form a priority encoded enabling for interrupts in the interrupt request 2 register. priority is generated by setting bits in each register. table 53 describes the priority control for irq2. pwmtenh?pwm timer interrupt request enable high bit u1renh?uart 1 receive interrupt request enable high bit u1tenh?uart 1 transmit interrupt request enable high bit pwmfenh? pwm fault interrupt request enable high bit c x enh/dmaxenh?port c x or dmax interrupt request enable high bit table 53. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 01level 1low 1 0 level 2 nominal 1 1 level 3 high note: x indicates the register bits from 0 through 7. table 54. irq2 enable high bit register (irq2enh) bits 7 6 5 4 3 2 1 0 field pwmtenh u1renh u1tenh pwmfenh c3enh/ dma3enh c2enh/ dma2enh c1enh/ dma1enh c0enh/ dma0enh reset 0000 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_e03ah www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 94 pwmtenl?pwm timer interrupt request enable low bit u1renl?uart 1 receive interru pt request enable low bit u1tenl?uart 1 transmit interru pt request enable low bit pwmfenl? pwm fault interrupt request enable low bit c x enl/dmaxenl?port c x or dmax interrupt request enable low bit. table 55. irq2 enable low bit register (irq2enl) bits 7 6 5 4 3 2 1 0 field pwmtenl u1renl u1tenl pwmfenl c3enl/ dma3enl c2enl/ dma2enl c1enl/ dma1enl c0enl/ dma0enl reset 0000 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_e03bh www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y interrupt controller zneo ? Z16F series product specification 95 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 96 timers the zneo ? Z16F series contains three 16-bit relo adable timers used for timing, event counting, or generation of pulse width modulated (pwm) signals. features the timers include the following features: ? 16-bit reload counter. ? programmable prescaler with values ranging from 1 to 128. ? pwm output generation (single or differential). ? capture and compare capability. ? external input pin for event counting, clock gating, or capture signal. ? complementary timer output pins. ? timer interrupt. architecture capture and compare capability measures the ve locity from a tachometer wheel or reads sensor outputs for rotor position fo r brushless dc motor commutation. figure 19 displays the architecture of the timer. figure 19. timer block diagram 16-bit pwm / compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer tout timer block system timer data block control bus clock input gate input capture input tout interrupt www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 97 operation the general-purpose timer is a 16-bit up-counter. in normal operation, the timer is initialized to 0001h . when the timer is enabled, it counts up to the value contained in the reload high and low byte registers, then resets to 0001h . the counter either halts or continues depending on the mode. minimum time-out delay ( 1 system clock ) is set by loading the value 0001h into the timer reload high and low byte register s and setting the prescale value to 1. maximum time-out delay ( 2 16 * 2 7 system clocks ) is set by loading the value 0000h into the timer reload high and low byte register s and setting the prescale value to 128. when the timer reaches ffffh , the timer rolls over to 0000h . if the reload register is set to a value less than the current coun ter value, the counter continues counting until it reaches ffffh , and then resets to 0000h . then the timer continues to count until it reaches the reload value and it resets to 0001h . when t0in0, t0in1, and t0in2 functions are enabled on the pb0, pb1, and pb2 pins, each timer0 input will have the same effect as the single timer0 input pin t0in. for example, if the timer 0 is in capture mode, any transitions on any of the pb0, pb1, and pb2 pins will cause a capture . timer operating modes the timers are configured to op erate in the following modes: one-shot mode in one-shot mode, the timer counts up to th e 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. when the timer reaches the reload value, it generates an inte rrupt and the count value in the timer high and low byte registers is reset to 0001h . the timer is automatically disabled and stops counting. if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high then ba ck to low if tpol = 0) at timer reload. if the timer output is required to make a pe rmanent state change on one-shot timeout, first set the tpol bit in the timer control 1 re gister to the start value before beginning one-shot mode. then, after starting the timer, set tpol to the opposite value. follow the steps below to configure a timer for one-shot mode and initiate the count: 1. write to the timer control registers to: ? disable the timer. ? configure the timer for one-shot mode. ? set the prescale value. note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 98 ? set the initial output level (high or low) using the tpol bit for the timer output alternate function. ? set the interrupt mode. 2. write to the timer high and low byte re gisters to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if required, and set the timer interrupt priority by writing to the relevant interrupt registers. 5. when using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control 1 register to enable the timer and initiate counting. the timer period is calculated by the following equation (start value = 1): triggered one-shot mode in triggered one-shot mode, the timer operates as follows: 1. the timer is non-active until a trigger is received. the tim er trigger is taken from the timer input pin. the tpol bit in the timer co ntrol 1 register selects whether the trigger occurs on the rising edge or the fa lling edge of the timer input signal. 2. following the trigger event, the timer coun ts system clocks up to the 16-bit reload value stored in the timer reload high and low byte registers. 3. after reaching the reload value, the timer outputs a pulse on the timer output pin, generates an interrupt, and resets the coun t value in the timer high and low byte registers to 0001h . the duration of the output pulse is a single system clock. the tpol bit also sets the pola rity of the output pulse. 4. the timer now idles until the next trigger event. trigger events, which occur while the timer is responding to a pr evious trigger is ignored. follow the steps below to configure timer 0 in triggered one-shot mode and initiate operation: 1. write to the timer control registers to: ? disable the timer ? configure the timer for triggered one-shot mode ? set the prescale value ? set the initial output level (high or lo w) via the tpol bit for the timer output alternate function ? set the interrupt mode one-shot mode time-out period (s) reload value start value + 1 ? () prescale system clock frequency (hz) ---------------------------------------------------------------------------------------------------------- = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 99 2. write to the timer high and low byte re gisters to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if required, and set the timer interrupt priority by writing to the relevant interrupt registers. 5. when using the timer output function, conf igure the associated gpio port pin for the timer output alternate function. 6. write to the timer control 1 register to en able the timer. counting does not start until the appropriate input transition occurs. the timer period is calculated by the following equation (start value = 1): continuous mode in continuous mode, the timer counts up to the 16-bit reload va lue stored in the timer reload high and low byte registers. after reaching the relo ad value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the timer output alternate function is enabled, the timer output pin changes state (from low to high or high to low) after timer reload. follow the steps below to configure a timer for continuous mode and initiate count: 1. write to the timer control registers to: ? disable the timer. ? configure the timer for continuous mode. ? set the prescale value. ? set the initial output level (high or low) through tpol for the timer output alternate function. 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this only affects the first pass in continuous mode. after the first timer reload in continuous mode, counting al ways begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload period. 4. enable the timer interrupt, if required, and set the timer interrupt priority by writing to the relevant interrupt registers. 5. when using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control 1 register to enable the timer and initiate counting. the timer period is calculated by the following equation: triggered one-shot mode time-out period (s) reload value start value + 1 ? () prescale system clock frequency (hz) ---------------------------------------------------------------------------------------------------------- = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 100 if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equation to determine the first timeout period. counter and comparator counter modes in counter mode, the timer co unts input transitions from a gpio port pin. the timer input is taken from the associated gpio port pin. the tpol bit in the timer control 1 register selects whether the coun t occurs on the rising edge or the falling edge of the timer input signal. in counter mode, the prescaler is disabled. the input frequency of the timer input sign al must not exceed one-fourth the sys - tem clock frequency. in comparator counter mode, the timer co unts output transitions from an analog comparator output. the timer takes its input from the output of the comparator. the tpol bit in the timer control 1 register selects whethe r the count occurs on the rising edge or the falling edge of the comparator output si gnal. the prescaler is disabled in the comparator counter mode. the frequency of the comparator output signal must not exceed one-fourth the system clock frequency. after reaching the reload value stored in the timer reload high and lo w byte registers, the timer generates an interrupt. the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the timer output alte rnate function is enabled, the timer output pin changes state (from low to high or high to low) at timer reload. follow the steps below to configure a timer for counter and comparator counter modes and initiate the count: 1. write to the timer control registers to: ? disable the timer. ? configure the timer for counter or comparator counter mode. ? select either the rising edge or falling ed ge of the timer input or comparator output signal for the count. this also sets th e initial logic level (high or low) for the timer output alternate function. however, you need not enable the timer output function. continuous mode time-out period (s) r e l oa d v a l ue p resca l e system clock frequency (hz) ---------------------------------------------------------------------------- = caution: caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 101 2. write to the timer reload high and low byte registers to set the starting count value. this affects only the first pass in the co unter modes. after the first timer reload, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function (counter mode). 6. when using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control 1 register to enable the timer. pwm single and dual output modes in pwm single output mode, the timer outputs a pwm output signal through a gpio port pin. in pwm dual output mode , the timer outputs a pwm output signal and also its complement through two gpio po rt pins. the timer first counts up to the 16-bit pwm match value stored in the timer pw m high and low byte registers. when the timer count value matches the pwm value, the timer output toggles. the timer continues counting until it reaches the reload value stor ed in the timer reload high and low byte registers. when it reaches the reload value, the timer generates an interrupt. the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the timer output signal begins with value = tpol and then transits to tpol , when the timer value matches the pwm value. th e timer output signal returns to tpol after the timer reaches the reload value and is reset to 0001h . in pwm dual output mode, the timer also generates a second pwm output signal, timer output complement (tout ). a programmable deadband is configured ( pwmd field) to delay (0 to 128 system clock cycles) the low to a high (inactive to active) output transitions on these two pins. this conf iguration ensures a time gap between the deassertion of one pwm output to the assertion of its complement. follow the steps below to configure a tim er for pwm single or dual output mode and initiate the pwm operation: 1. write to the timer control registers to: ? disable the timer. ? configure the timer for the selected pwm mode. ? set the prescale value. ? set the initial logic level (high or low) and pwm high or low transition for the timer output alternate function with the tpol bit. ? set the deadband delay (dual output mode) with the pwmd field. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 102 2. write to the timer high and lo w byte registers to set the st arting count value (typically 0001h ). the starting count value only affect s the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. enable the timer interrupt, if required, and set the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin(s) for the timer output alternate function. 7. write to the timer control 1 register to enable the timer and initiate counting. the pwm period is determined by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equation to determine the first pwm timeout period. if tpol is set to 0, the ratio of the pwm output high time to the total period is determined by: if tpol is set to 1, the ratio of the pwm output high time to the total period is determined by: capture modes there are three capture modes which provide slightly different methods for recording the time or time interval between timer in put events. these modes are capture mode, capture restart mode, and capture comp are mode. in all the three modes, when the appropriate timer input transition (cap ture event) occurs, the timer counter value is captured and stored in the pwm high and low byte register s. the tpol bit in the timer control 1 register determines if the capture occu rs on a rising edge or a falling edge of the timer input signal. the ticonfig bit determ ines whether interrupts are generated on capture events, reload events, or both. the in cap bit in timer control 0 register clears to indicate an interrupt caused by a reload event and sets to indicate the timer interrupt is caused by an input capture event. pwm period (s) reload value prescale system clock frequency (hz) ---------------------------------------------------------------------------- = pwm output high time ratio (%) reload value pwm value ? reload value ----------------------------------------------------------------------- - 100 = pwm output high time ratio (%) pwm value reload value ---------------------------------- 100 = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 103 if the timer output alte rnate function is enabled, the timer output pin changes state (from low to high or high to low) at timer re load. the initial value is determined by the tpol bit. capture mode when the timer is enabled in capture mode , it counts continuously and resets to 0000h from ffffh . when the capture event occurs, the timer counter value is captured and stored in the pwm high and low byte register s, an interrupt is ge nerated and the timer continues counting. the timer co ntinues counting up to the 16 -bit reload value stored in the timer reload high and low byte registers. on reaching the reload valu e, the timer generates an interrupt and continues counting. capture restart mode when the timer is enabled in capture r estart mode, it counts continuously until the capture event occurs or the timer count re aches the 16-bit compare value stored in the timer reload high and low byte registers. if the capture event occurs first, the timer counter value is captured and st ored in the pwm high and low byte registers, an interrupt is generated and the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if no capture event occu rs, on reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. capture/compare mode the capture/compare mode is identical to capture restart mode except that counting does not start until the first appropriat e external timer reload high and low byte input transition occurs. every su bsequent appropriate transition (after the first) of the timer reload high and low byte input signal captures the current count value. when the capture event occurs, an interru pt is generated, the count value in the timer reload high and low byte high and low byte registers is reset to 0001h , and counting resumes. if no capture event occurs, on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. follow the steps below to configure a timer for one of the capture modes and initiate the count: 1. write to the timer control registers to: ? disable the timer. ? configure the timer for the selected capture mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 104 ? configure the timer interrupt to be genera ted at the input capture event, the reload event or both by setting ticonfig field. 2. write to the timer reload high and low by te registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control 1 register to enable the timer. in capture and capture restart modes, the timer begins counting. in capture compare mode the timer does not start counting until the fi rst appropriate inpu t transition occurs. in capture modes, the elapsed time from timer start to capture event is calculated using the following equa tion (start value = 1): compare mode in compare mode, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. after re aching the compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001h ). if the timer output alternate function is en abled, the timer output pin ch anges state (from low to high or high to low). if the timer reaches ffffh , the timer rolls over to 0000h and continues counting. follow the steps below to configure timer for compare mode and initiate the count: 1. write to the timer control registers to: ? disable the timer. ? configure the timer for compare mode. ? set the prescale value. ? set the initial logic level (high or low) for the timer output alternate function, if required. 2. write to the timer high and low byte re gisters to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers. 5. when using the timer output function, configure the associated gpio port pin for the timer output alternate function. capture elapsed time (s) capture value start value + 1 ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 105 6. write to the timer control 1 register to enable the timer and initiate counting. the compare time is calcu lated by the following equa tion (start value = 1): gated mode in gated mode, the timer counts only when the timer input sign al is in its active state as determined by the tpol bit in the timer control 1 register. when the timer input signal is active, counting begins. a timer interrupt is ge nerated when the timer input signal transits from active to inactive state or a timer reload occurs. to dete rmine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16-b it reload value stored in the timer reload high and low byte registers. on reaching the reload value, the tim er generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting continues as long as the timer input signal is active. if the timer output alternate function is enab led, the timer output pin changes state (from low to high or from high to low) at timer reload. follow the steps below to configure a timer for gated mode and initiate the count: 1. write to the timer control registers to: ? disable the timer ? configure the timer for gated mode ? set the prescale value ? select the active state of the tim er input through the tpol bit 2. write to the timer high and low byte register s to set the initial count value. this affects only the first pass in gated mode. afte r the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the timer interrupt to be genera ted only at the input deassertion event, the reload event, or both by setting ticonfig field of the timer control 0 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control 1 register to enable the timer. 8. the timer counts when the time r input is equal to the tpol bit. compare mode time (s) compare value start value + 1 ? () prescale system clock frequency (hz) ---------------------------------------------------------------------------------------------------------------- = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 106 reading timer count values the current count value in the tim er is read while counting (enabled). this has no effect on timer operation. normally, the count must be read with on e 16-bit operation. however, 8 bit reads are done with th e following method. when the timer is enabled and the timer high byte register is read, the contents of the timer low byte register are placed in a holding register. a subsequent read from the timer lo w byte register returns the value in the holding register. this operatio n allows accurate reads of th e full 16-bit timer count value when enabled. when the timer is not enable d, a read from the timer low byte register returns the actual va lue in the counter. the timers can be cascaded by using the cascad e bit in the timer control registers. when this bit is set for a timer, the input source is redefined. when the cascade bit is set for timer0, the input for timer0 is the output of the analog comparator. when the cascade bit is set for timer1 and timer2, the output of timer0 and timer1 become the input for timer1 and timer2, respectively. any timer mode can be used. timer0 can be cascaded to timer1 only by setting the cascade bit for timer1. timer1 cascaded to timer2 only by setting the cascade bit for timer2. or all thre e cascaded, timer0 to ti mer1 or timer2 for really long counts by setting the cascade bit for timer1 and timer2. timer control register definitions timer 0-2 high and low byte registers the timer 0-2 high and low byte (txh and txl) registers (see table 56 and table 57 ) contain the current 16-bit timer count value. when the timer is enabled, a read from txh stores the value in txl to a temporary holdin g register. a read from txl always returns this temporary register when the timer is enabled. when the timer is disabled, reads from the txl reads the register directly. writing to the timer high and low byte regi sters while the timer is enabled is not recommended. there are no tem porary holding registers available for write operations, so simultaneous 16-bit writes are not possible. wh en either of the timer high or low byte registers are written during counting, the 8-bit written value is placed in the counter (high or low byte) at the next clock edge. the co unter continues counti ng from the new value. table 56. timer 0-2 high byte register (txh) bits 7 6 5 4 3 2 1 0 field th reset 00h r/w r/w addr ff-e300h, ff-e310h, ff-e320h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 107 th and tl?timer high and low bytes these two bytes, {th[7:0], tl[7:0]}, contai n the current 16-bit timer count value. timer x reload high a nd low byte registers the timer 0-2 reload high and low byte (txrh and txrl) registers (see table 58 and table 59 ) store a 16-bit reload valu e, {trh[7:0], trl[7:0]}. values written to the timer reload high byte register are stored in a te mporary holding register. when a write to the timer reload low byte register occurs, the temp orary holding register value is written to the timer high byte register. this operation a llows simultaneous update s of the 16-bit timer reload value. trh and trl?timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[ 7:0]}. this value sets the maximum count valu e which initiates a timer reload to 0001h . table 57. timer 0-2 low byte register (txl) bits 7 6 5 4 3 2 1 0 field tl reset 01h r/w r/w addr ff-e301h, ff-e311h, ff-e321h table 58. timer 0-2 reload high byte register (txrh) bits 7 6 5 4 3 2 1 0 field trh reset ffh r/w r/w addr ff-e302h, ff-e312h, ff-e322h table 59. timer 0-2 reload low byte register (txrl) bits 7 6 5 4 3 2 1 0 field trl reset ff r/w r/w addr ff-e303h, ff-e313h, ff-e323h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 108 timer 0-2 pwm high and low byte registers the timer 0-2 pwm high and low byte (txpwmh and txpwml) registers ( table 60 and table 61 on page 108) define pwm operations. these registers also store the timer counter values for the capture modes. pwmh and pwml?pulse-width modulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, fo rm a 16-bit value which is compared to the current 16-bit timer count. when a match occurs, the pw m output changes state. the pwm output value is set by the tpol bit in the timer control 1 register (txctl1). the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. timer 0-2 control registers timer 0-2 control 0 register the timer 0-2 control 0 (txctl0) register together with timer 0-2 control 1 (txctl1) register determines the timer configuration and operation. table 60. timer 0-2 pwm high byte register (txpwmh) bits 7 6 5 4 3 2 1 0 field pwmh reset 00h r/w r/w addr ff-e304h, ff-e314h, ff-e324h table 61. timer 0-2 pwm low byte register (txpwml) bits 7 6 5 4 3 2 1 0 field pwml reset 00h r/w r/w addr ff-e305h, ff-e315h, ff-e315h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 109 table 62. timer 0-2 control 0 register (txctl0) bits 7 6 5 4 3 2 1 0 field tmode[3] ticonfig cascade pwmd incap reset 0 00 0 000 0 r/w r/w r/w r/w r/w r addr ff-e306h, ff-e316h, ff-e326h bit position value (h) description [7] tmode[3] timer mode high bit this bit along with tmode[2:0] field in t0ctl1 register determines the operating mode of the timer. this is the most significant bit of the timer mode selection value. for more details, see the t0ctl1 register description. [6?5] ticonfig timer interrupt configuration ?this field configures timer interrupt definitions. these bits affect all modes. the effect per mode is explained below: one shot, continuous, counter, pwm, compare, dual pwm, triggered one-shot, comparator counter: 0x timer interrupt occurs on reload. 10 timer interrupts are disabled. 11 timer interrupt occurs on reload. gated : 0x timer interrupt occurs on reload. 10 timer interrupt occurs on inactive gate edge. 11 timer interrupt occurs on reload. capture, capture/compare, capture restart : 0x timer interrupt occurs on reload and capture. 10 timer interrupt occurs on capture only. 11 timer interrupt occurs on reload only. [4] cascade 0 1 timer cascade ?this field allows the timers to be cascaded for larger counts. only counter mode must be used with this feature. the timer is not cascaded. timer is cascaded. if timer 0 cascad e bit is set, analog comparator output is used as input. if timer 1 c ascade bit is set, th e timer 0 output is used as the input. if timer 2 cascade bit is set, the timer 1 output is used as input. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 110 timer 0-2 control 1 register the timer 0-2 control 1 (txctl1) register en ables/disables the timer, sets the prescaler value, and determines th e timer operating mode. [3:1] pwmd 000 001 010 011 100 101 110 111 pwm delay value this field is a programmable delay to co ntrol the number of additional system clock cycles following a pwm or reload compare before the timer output or the timer output complement is switched to the active state. this field ensures a time gap between deassertion of o ne pwm output to the assertion of its complement. no delay. 2 cycles delay. 4 cycles delay. 8 cycles delay. 16 cycles delay. 32 cycles delay. 64 cycles delay. 128 cycles delay. [0] incap 0 input capture event previous timer interrupt is not a re sult of a timer input capture event. 1 previous timer interrupt is a resu lt of a timer input capture event. table 63. timer 0-2 control 1 register (txctl1) bits 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 0 0 000 000 r/w r/w r/w r/w r/w addr ff-e307h, ff-e317h, ff-e327h bit position value (h) description [7] ten 0 timer is disabled. 1 timer is enabled. note: ten bit is cleared automatically when the timer stops. bit position value (h) description www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 111 [6] tpol timer input/output polarity this bit is a function of the curren t operating mode of the timer. it determines the polarity of the input an d/or output signal. when the timer is disabled, the timer output signal is set to the value of this bit. one-shot mode ?if the timer is enabled, the timer output signal pulses (changes state) for one system clock cycle after timer reload. continuous mode ?if the timer is enabled, the timer output signal is complemented after timer reload. counter mode ?if the timer is enabled, the timer output signal is complemented after timer reload. 0 = count occurs on the rising edge of the timer input signal. 1 = count occurs on the falling ed ge of the timer input signal. pwm single output mode ?when enabled, the timer output is forced to tpol after pwm count match and forced back to tpol after reload. capture mode ?if the timer is enabled, the timer output signal is complemented after timer reload. 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the falling edge of th e timer input signal. compare mode ?the timer output signal is complemented after timer reload. gated mode ?the timer output signal is complemented after timer reload. 0 = timer counts when the timer input signal is high and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the timer input signal is low and interrupts are generated on the rising edge of the timer input. capture/compare mode ?if the timer is enab led, the timer output signal is complemented after timer reload. 0 = counting starts on the first rising edge of the timer input signal. the current count is captured on s ubsequent rising edges of the timer input signal. 1 = counting starts on the first fa lling edge of the timer input signal. the current count is captured on s ubsequent falling edges of the timer input signal. bit position value (h) description www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 112 pwm dual output mode ? if enabled, the timer output is set=tpol after pwm match and set = tpol af ter reload. if enabled the timer output complement takes on the oppos ite value of the timer output. the pwmd field in the t0ctl1 register determines an optional added delay on the assertion (low to high) transition of both timer output and the timer output complement for deadband generation. capture restart mode ? if the timer is enabled, the timer output signal is complemented after timer reload. 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the falling edge of the timer input signal. analog comparator counter mode ? if the timer is enabled, the timer output signal is complemented after timer reload. 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the falling edge of the timer input signal. triggered one-shot mode ? if the timer is enabled, the timer output signal is complemented after timer reload. 0 = the timer triggers on a low to high transition on the input. 1 = the timer triggers on a high to low transition on the input. [5?3] pres 000 001 010 011 100 101 110 111 the timer input clock is divided by 2 pres , where pres is set from 0 to 7. the prescaler is reset each time the timer is disabled. this ensures proper clock division each time the timer is restarted. divide by 1 divide by 2 divide by 4 divide by 8 divide by 16 divide by 32 divide by 64 divide by 128 [2?0] tmode[2:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 this field along with the tmode[3] bit in t0ctl0 register determines the operating mode of the time r. tmode[3:0] selects from the following modes: one-shot mode continuous mode counter mode pwm single output mode capture mode compare mode gated mode capture/compare mode pwm dual output mode capture restart mode comparator counter mode triggered one-shot mode bit position value (h) description www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y timers zneo ? Z16F series product specification 113 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 114 multi-channel pwm timer the zneo ? Z16F series includes a multi-channel pwm optimized for motor control applications. the pwm incl udes the following features: ? six independent pwm outputs or thr ee complementary pwm output pairs. ? programmable deadband insertion for complementary output pairs. ? edge-aligned or center-aligned pwm signal generation. ? pwm off-state is an option bit programmable. ? pwm outputs driven to o ff-state on system reset. ? asynchronous disabling of pwm outputs on system fault. outputs are forced to off-state. ? fault inputs generate pulse-by-pulse or hard shutdown. ? 12-bit reload counter with 1, 2, 4, or 8 programmable clock prescaler. ? high current source and sink on all pwm outputs. ? pwm pairs used as general purpose inputs when outputs are disabled. ? adc synchronized with pwm period. ? synchronization for current -sense sample and hold. ? narrow pulse suppression with programmable threshold. architecture the pwm unit consists of a master timer to generate the modulator time base and six independent compare registers to set th e pwm for each output. the six outputs are designed to provide control sign als for inverter drive circuits . the outputs are grouped into pairs consisting of a high-side driver and a lo w-side driver output. the output pairs are programmable to operate independently or as complementary signals. in complementary output mode, a programmab le dead-time is inserted to ensure non- overlapping signal transitions. the master coun t and compare values feed into modulator logic which generates the proper transitions in the output states. output polarity and fault/ off-state control logic allows programming of the default off-sta tes which forces the outputs to a safe state in the event a fault in the motor drive is detected. figure 20 on page 115 displays the architecture of the pwm modulator. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 115 figure 20. pwm block diagram operation pwm option bits to protect the configuration of critical pwm parameters, settings to enable output channels and the default off-state are maintain ed as user option bits. these values are set when the user program code is written to the part and the software cannot chan ge these values (see option bits on page 293). 12-bit counter with prescaler pwm deadband pwmh0d pwml0d pwmh1d pwml1d pwmh2d pwml2d fault polarity logic fault inputs pwmh0 pwmh1 pwml0 pwml2 pwmh2 pwml1 data bus system clock pwm state logic control logic pwm state logic pwm state logic fault polarity logic fault polarity logic isense s/h irq adc trig www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 116 pwm output polarity and off-state the default off-state and polar ity of the pwm outputs are co ntrolled by the option bits pwmhi and pwmlo. the pwmhi option contro ls the off-state and polarity for pwm high-side outputs pwmh0, pwmh1, and pwmh2. the pwmlo option controls the off-state and polarity for low-side outputs pwml0, pwml1, and pwml2. the off-state is the value programmed in the option bit. for example, programming pwmhi to 1 makes the off-state of pwmh0, pwmh 1, and pwmh2 a high logic value and the active state a low logic value. conversely, programming pwmhi to 0 causes the off-state to be a low logic value. pwmlo is programmed in a similar manner. pwm enable the mcen option bit enables output pair s pwm0, pwm1, and pwm2. if the motor control option is not enabled, the pwm output s remain in a high-impedance state after reset and is used as alternat e functions like general purpose input. if the motor control option is enabled, following a power-on reset (por) the pwm pins enter a high impedance state. as the internal reset pro ceeds, the pwm outputs are forced to the off- state as determined by the pwmh i and pwmlo off-state option bits. pwm reload event to prevent erroneous pwm pulse-widths and periods, registers that control the timing of the output are buffered. buffering causes all th e pwm compare values to update. in other words, the registers controlling the duty cycle, and clock sour ce prescaler only take effect on a pwm reload event. a pwm reload event is configured to occur at the end of each pwm period or only every 2, 4, or 8 pwm periods by setting the relfreq bits in the pwm control 1 register (pwmctl1) . software indicates that all new values are ready by setting the ready bit in the pwm control 0 register (pwmctl0) to 1. when the ready bit is set to 1, the buffered values take effect at the next reload event. pwm prescaler the prescaler decreases the pwm clock signal by fa ctors of 1, 2, 4, or 8 with respect to the system clock. the pres[1:0] bit field in the pwm control 1 register (pwmctl1) controls prescaler operation. this 2-bit pres field is buffered so that the prescale value only changes on a pwm reload event. pwm period and count resolution the pwm counter operates in two modes to allow edge-aligned and center-aligned outputs. figure 21 and figure 22 on page 117 illustrate edge and center-aligned pwm outputs. the mode in which the pwm operates determine the period of the pwm outputs www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 117 (period). the programmed duty-cycle (p wmdc) and the programmed deadband time (pwmdb) determine the active time of a pw m output. the following sections describe the pwm timer modes and the registers cont rolling the duty-cycle and deadband time. figure 21. edge-aligned pwm output figure 22. center-aligned pwm output pwm xh n o d ea d b an d pwml x pwml x pwm hx d ea d b an d in s erti o n pwm db pwm d c pwm db peri od pwmdb no dead band dead band insertion pwmdc pwmdb pwmhx pwmlx pwmhx pwmlx period www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 118 edge-aligned mode in edge-alinged pwm mode, a 12-bit up counter creates the pwm period with a minimum resolution equal to the pwm clock source period. the counter counts up to the reload value, resets to 000h , and then resumes counting. center-alinged mode in center-alinged pwm mode, a 12-bit up /down counter creates the pwm period with a minimum resolution eq ual to twice the pwm clock source period. the counter counts up to the reload valu e and then counts down to 0. pwm duty cycle registers the pwm duty cycle registers (pwmh0d, pwml0d, pwmh1d, pwml1d, pwmh2d, pwml2d) contain a 16-bit signed value where bit 15 is the sign bit. the duty cycle value is compared to the current 12 -bit unsigned pwm count value. if the pwm duty cycle value is set less than or equal to 0, the pwm output is deasserted for full pwm period. if the pwm duty cycle va lue is set to a value greater than the pwm reload value, the pwm output is asserted for full pwm period. independent and complementary pwm outputs the six pwm outputs are configured to operate independently or as three complementary pairs. operation as six independent pwm ch annels are enabled by setting the inden bit in the pwm control 1 register (pwmctl1) . in independent mode, each pwm output uses its own pwm duty cycle value. when pwm outputs are configured to operat e as three complement ary pairs, the pwm duty cycle values pwmh0d, pwmh1d, and pwmh2d control the modulator output. in complementary output mode dead band time is also inserted. the polx bits in the pwm control 1 register (pwmctl1) select the relative polarity of the high- and low-side signals. as illustrated in figure 21 and figure 22 on page 117, when the polx bits are cleared to 0, the pwm high-side output will start in the on-state and transits to the off-state when the p wm timer count reaches the programmed duty cycle. the low-side pwm value st arts in the off-state and tran sits to the on-state as the pwm timer count reaches the value in the asso ciated duty cycle register. alternately, setting the polx causes the high-side output to start in the off-state and the low-side output to start in the on-state. edge-aligned pwm mode period prescaler reload value f pwmclk -------------------- --------------------- ------------------- - = center-aligned pwm mode period 2 prescaler reload value f pwmclk ------------------ ------------------ ----------------- ---------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 119 manual off-state control of pwm output channels each pwm output is controlled directly by th e modulator logic or set to the off-state. to manually set the pwm output to the off-state, set the outctl bit and the associated outx bits in the pwm output control register (pwmout) . off-state control operates individually by channel. for example, supp ressing a single output of pair allows the complementary channel to continue operatin g. similarly, if the outputs are operating independently disabling one output channel has no effect on the other pwm outputs. deadband insertion when the pwm outputs are configured to op erate as complementary pairs, an 8-bit deadband value is defined in the pwm deadband register (pwmdb) . inserting deadband time causes the modulator to separate th e deassertion of one pwm signal from the assertion of its complement. this is essentia l for many motor cont rol applications to prevent simultaneous turn-on of the high-s ide and low-side drive transistors. the deadband counter directly counts system cloc k cycles and is unaffected by pwm prescaler settings. the width of this deadband is the nu mber of system clock cycles specified in the pwm deadband register (pwmdb) . the minimum deadband duration is zero system clocks and the maximum time is 255 sy stem clocks. both pwm outputs of a complementary pair is deasserted during the deadband period. generation of deadband time does not alter the pwm pe riod but the deadband time is subtracted from the active time of the pwm outputs. figure 21 on page 117 displays the effect of deadband insertion on the pwm output. minimum pwm pulse width filter the pwm modulator is capable of producin g pulses as narrow as a single system clock cycle in width. the response time of external dr ive circuit is slower than the period of a system clock. therefore, a filter is implemen ted to enforce a minimu m width pulse on the pwm output pins. all output pulses, either high or low, must be at least the minimum number of pwm clock cycles (for more details, see pwm prescaler on page 116) in width as specified in the pwm minimum pulse width filter (pwmmpf) register. if the expected pulse width is less than the thre shold, the associated pwm output does not change state until the duty cy cle value has changed sufficien tly to allow pulse generation of an acceptable width. the minimum pulse wi dth filter also accounts for the duty cycle variation caused by the deadband insertion. the pwm output pulse is filtered even if the programmed duty cycle is greater than th e threshold but the decrease in pulse width because of deadband insertion causes the pul se to be too narrow. the pulse width filter value is calculated as: where is the shortest allowed pulse widt h on the pwm outputs (in seconds). roundup pwmmpf () t minpulseout t systemclock pwmprescaler ? () ? = t minpulseout www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 120 synchronization of pwm and adc the adc on the zneo is synchronized w ith the pwm period. enabling the pwm adc trigger causes the pwm to generate an adc co nversion signal at the end of each pwm period. additionally, in center-alinged mo de, the pwm generates a trigger at the center of the period. settin g the adctrig bit in the pwm control 0 register (pwmctl0) enables the adc synchronization. synchronized current-s ense sample and hold the pwm controls the current-sense input sa mple and hold amplifier. the signal controlling the sample/hold is configured to always sample or auto matically hold when any or all the pwm high or low outputs are in the on state. the current-sense sample and hold is controlled by the current-sense sample and hold control register (csshr0 and csshr1) . pwm timer and fault interrupts the pwm generates interrupts to the zneo cpu during any of the following events: ? pwm reload ?the interrupt is generated at the end of a pwm period when a pwm register reload occurs. ? pwm fault ?a fault condition is indicated by asserting any fault pins or by the assertion of the comparator. fault detection and protection the zneo contains hardware and software fault controls, which allow rapid deassertion of all enabled pwm output signals. a logic low on an external fault pin (fault0 or fault1) or the assertion of the over current comparator forces th e pwm outputs to the predefined off-state. similar deassertion of the pwm outputs is accomplished in software by writing to the pwmoff bit in the pwm cont rol 0 register. the pwm counter continues to operate while the outputs are deasserted (inactive) due to one of these fault conditions. the fault inputs are individually enabled thro ugh the pwm fault contro l register. if a fault condition is detected and the source is enab led, the fault interrupt is generated. the pwm fault status register (pwmfstat) is read to determine wh ich fault source caused the interrupt. when a fault is detected and the pwm outp uts are disabled, modulator control of the pwm outputs are reenabled either by the softwa re or by the fault input signal deasserting. selection of the reenable method is made using the pwm fault control register (pwmfctl) . configuration of the fault m odes and reenable methods allow www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 121 pulse-by-pulse limiting and hard shutdo wn. when configured in automatic restart mode, the pwm outputs are re-engag ed at beginning of the next pwm cycle (master timer value is eq ual to 0) if all fault signals are deasserted. in software controlled restart, all fault inputs must be deasser ted and the fault flags must be cleared. the fault input pin is schmitt- triggered. the input signal from the pin as well as the comparators pass though an analog filte r to reject high-frequency noise. the logic path from the fault so urces to the pwm output is as ynchronous ensuring that the fault inputs forces the pwm outp uts to their off-state even if the system clock is stopped. pwm operation in cpu halt mode when the zneo cpu is opera ting in halt mode, the pwm cont inues to operate if it is enabled. to minimize current in halt mo de, the pwm must be disabled by clearing the pwmen bit to 0. pwm operation in cpu stop mode when the zneo cpu is opera ting in stop mode, the pwm is disabled as the system clock ceases to operate in stop mode. the pwm output remains in the same state as they were prior to entering the stop mode. in normal operation, the pwm outputs must be disabled by software prior to the cpu ente ring the stop mode. a fa ult condition detected in stop mode forces the pwm outp uts to the predefined off-state. observing the state of pwm output channels the logic value of the pwm outputs is sam pled by reading the pwmin register. if a pwm channel pair is disabled (option bit is not set), the associated pwm outputs are forced to high impedance and are used as general purpose inputs. pwm control register definitions the following sections describe th e various pwm control registers. pwm high and low byte registers the pwm high and low byte (pwmh and pwml) registers (see table 64 and table 65 ) contain the current 12-bit pwm count value. reads from pwmh stores the value in pwml to a temporary holding register. a read from pwml always returns this temporary register value. it is not recommended to wr ite to the pwm high and low byte registers when the pwm is enabled. there are no temp orary holding registers for write operations, so simultaneous 12-bit writes are not possible. when either the pwm high and low byte registers are written during counting, the 8-bit written value is placed in the counter (high or low byte) at the next clock edge. the counter continues coun ting from the new value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 122 pwmh and pwml?pwm high and low bytes these two bytes, {pwmh[3:0], pwml[7:0]} , contain the current 12-bit pwm count value. pwm reload high and low byte registers the pwm reload high and low byte (pwmrh and pwmrl) registers (see table 66 and table 67 on page 123) store a 12-bit reload value, {pwmrh[3:0], pwmrl[7:0]}. the pwm reload value is held in buffer register s. the pwm reload value written to the buffer registers are not used by the pwm generato r until the next pwm reload event occurs. reads from these registers always return the values from the buffer registers. table 64. pwm high byte register (pwmh) bits 7 6 5 4 3 2 1 0 field reserved pwmh reset 0h 0h r/w r/w r/w addr ff_e38ch table 65. pwm low byte register (pwml) bits 7 6 5 4 3 2 1 0 field pwml reset 01h r/w r/w addr ff_e38dh edge-aligned pwm mode period prescaler reload value f pwmclk ---------------------- --------------------- ----------------- - = center-aligned pwm mode period 2 prescaler reload value f pwmclk ------------------- ------------------ ----------------- --------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 123 pwmrh and pwmrl?pwm reload register high and low these two bytes form the 12-b it reload value, {pwmrh[3:0], pwmrl[7:0]}. this value sets the pwm period. pwm 0-2 duty cycle high and low byte registers the pwm 0-2 h/l (high side/low side) duty cycle high and low byte (pwm x dh and pwm x dl) registers (see table 68 and table 69 on page 124) set the duty cycle of the pwm signal. this 14-bit signed value is compared to the pwm count value to determine the pwm output. reads from these registers always return the values from the temporary holding registers. the pwm generator does not use the pwm duty cycle value until the next pwm reload event occurs. writing a negative value (dutyh[7] = 1) fo rces the pwm to be off for the full pwm period. writing a positive value greater than the 12-bit pwm reload value forces the pwm to be on for the full pwm period. table 66. pwm reload high byte register (pwmrh) bits 7 6 5 4 3 2 1 0 field reserved pwmrh reset 0h fh r/w r/w r/w addr ff_e38eh table 67. pwm reload low byte register (pwmrl) bits 7 6 5 4 3 2 1 0 field pwmrl reset ff r/w r/w addr ff_e38fh pwm duty cycle 100 pwm duty cycle value pwm reload value -------------------- --------------------- ----------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 124 pwm control 0 register the pwm control 0 register (pwm ctl0) controls pwm operation. table 68. pwm 0-2 h/l duty cycle high byte register (pwmh x dh, pwml x dh) bits 7 6 5 4 3 2 1 0 field sign reserved dutyh reset x xx x_xxxx r/w r/w r/w r/w addr ff_e390h, ff_e392h, ff_e394h, ff_e396h, ff_e398h, ff_e39ah table 69. pwm 0-2 h/l duty cycle low byte register (pwmh x dl, pwml x dl) bits 7 6 5 4 3 2 1 0 field dutyl reset xxh r/w r/w addr ff_e391h, ff_e393h, ff_e395h, ff_e397h, ff_e399h, ff_e39bh bit position value (h) description [7] sign 0 duty cycle sign duty cycle is a positive two?s complement number. 1 duty cycle is a negative two?s complement number. output is forced to the off-state. [6:0], [7:0] dutyh and dutyl pwm duty cycle high and low bytes these two bytes, {dutyh[7:0], dutyl[7:0]}, form a 14-bit signed value (bits 5 and 6 of the high byte are always 0). the value is compared to the current 12-bit pwm count. table 70. pwm control 0 register (pwmctl0) bits 7 6 5 4 3 2 1 0 field pwmoff outctl align reserved adctrig reserved ready pwmen reset 00 000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_e380h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 125 bit position value (h) description [7] pwmoff 0 place pwm outputs in off-state disable modulator control of pwm pins. outputs are in predefined off-state. this is not dependent on the reload event. 1 re-enable modulator control of pwm pins at next pwm reload event. [6] outctl 0 pwm output control pwm outputs are controlled by the pulse-width modulator. 1 pwm outputs selectively disabled (set to off-state) according to values in the out x bits of the pwmout register. [5] align 0 pwm edge alignment pwm outputs are edge aligned. 1 pwm outputs are center aligned. [4] reserved reserved. [3] adctrig 0 adc trigger enable no adc trigger pulses. 1 adc trigger enabled. [2] reserved 0 reserved. [1] ready 0 values ready for next reload event pwm values (pre-scale, period, and duty cycle) are not ready. do not use values in holding registers at next pwm reload event. 1 pwm values (pre-scale, period, and duty cycle) are ready. transfer all values from temporary holding registers to working registers at next pwm reload event. [0] pwmen 0 pwm enable pwm is disabled and enabled pwm output pins are forced to default off- state. pwm master counter is stopped. 1 pwm is enabled and pwm output pins are enabled as outputs. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 126 pwm control 1 register the pwm control 1 (pwmctl1) register controls portions of pwm operation. table 71. pwm control 1 register (pwmctl1) bits 7 6 5 4 3 2 1 0 field rlfreq[1:0] inden pol45 pol23 pol10 pres[1:0] reset 00 0 0 00 00 r/w r/w r/w r/w r/w r/w r/w addr ff_e381h bit position value (h) description [7:6] rlfreq[1:0] 00 01 10 11 reload event frequency this bit field is buffered. changes to the reload event frequency takes effect at the end of the current pwm period. reads always return the bit values from the temporary holding register. pwm reload event occurs at the end of every pwm period. pwm reload event occurs once every two pwm periods. pwm reload event occurs once every four pwm periods. pwm reload event occurs once every eight pwm periods. [5] inden 0 independent pwm mode enable pwm outputs operate as three complementary pairs. 1 pwm outputs operate as six independent channels. [4] pol2 1 invert output polarity for channel pair pwm2. 0 non-inverted polarity for channel pair pwm2. [3] pol1 1 invert output polarity for channel pair pwm1. 0 non-inverted polarity for channel pair pwm1. [2] pol0 1 invert output polarity for channel pair pwm0. 0 non-inverted polarity for channel pair pwm0. [1:0] pres 00 01 10 11 pwm prescaler the prescaler divides down the pwm in put clock (either th e system clock or the pwmin external input). this field is buffered. changes to this field take effect at the next pwm reload event. reads always return the values from the temporary holding register. divide by 1 divide by 2 divide by 4 divide by 8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 127 pwm deadband register the pwm deadband (pwmdb) register (see table 72 ) stores the 8-bit pwm deadband value. the deadband value de termines the number of pwm input cycles to use for the deadband time for complementary pwm output pairs. when countin g pwm input cycles, the pwm input signal is used directly (no prescaler). the minimum deadband value is 1. maximum deadband time is prog rammed by setting a value of 00h . this register is written only once following a system reset event. all other writes are ignored. pwm minimum pulse width filter the value in the pwmmpf regist er determines the minimum wi dth pulse, either high or low, generated by the pwm module. the minimum pulse width period is calculated as: pwmmpf?minimum pulse filter sets the minimum allowed output pulse width in pwm clock cycles. table 72. pwm deadband register (pwmdb) bits 7 6 5 4 3 2 1 0 field pwmdb[7:0] reset 01h r/w r/w addr ff_e382h bit position value (h) description [7:0] pwmdb[7:0] pwm deadband sets the pwm deadband period for which both pwm outputs of a complementary pwm output pair are deasserted. table 73. pwm minimum pulse width filter (pwmmpf) bits 7 6 5 4 3 2 1 0 field pwmmpf[7:0] reset 00h r/w r/w addr ff_e383h t minpulseout pwmdb pwmmpf + t systemclock pwmprescale ? -------------------- ----------------- ------------------ -------------- = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 128 pwm fault mask register the pwm fault mask register, enables individual fault sources. when an input is asserted, pwm behavior is determined by the pwm fault control register (pwmfctl) . the pwm fault mask (pwmf) the comparator 0-3 outputs generate pwm faults and the associated fault system exception. the bits in this register only be set. all other writes are iged. table 74. pwm fault mask register (pwmfm) bits 7 6 5 4 3 2 1 0 field reserved dbgmsk reserv ed f1mask c0mask fmask reset 00 0 000 0 0 0 r/w r r/w1 r r/w1 r/w1 r/w1 addr ff_e384h bit position value (h) description [7:6] reserved must be 0 [5] dbgmsk 0 debug entry fault mask entering cpu debug mode generates a pwm fault. 1 entering cpu debug mode does not generate a pwm fault. [4:3] reserved must be 0 [2] f1mask 0 fault 1 fault mask fault 1 generates a pwm fault. 1 fault 1 does not generate a pwm fault. [1] c0mask 0 comparator fault mask comparator generates a pwm fault. 1 comparator does not generate a pwm fault. [0] f0mask 0 fault pin mask fault 0 pin generates a pwm fault. 1 fault 0 pin does not generate a pwm fault. note : this register is written to once, w1 only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 129 pwm fault status register the pwm fault status (pwmfstat ) register provides status of fault inputs and timer reload. the fault flags indicate the fault source , which is active. if a fault source is masked, the flag in this register is no t set when the source is asserted. the reload flag is set when the timer compare values are up dated. clear flags by writing 1 to the flag bits. fault flag bits are cleared only if the associated fault source has deasserted. table 75. pwm fault status register (pwmfstat) bits 7 6 5 4 3 2 1 0 field rldflag reserved dbgflag reserved f1flag c0flag fflag reset u0 u 00 uuu r/w r/w1c r r/w1c r r/w1c r/w1c r/w1c addr ff_e385h bit position value (h) description [7] rldflag reload flag this bit is set and latched when a pwm timer reload occurs. writing a 1 to this bit clears the flag. [6] reserved 0 reserved always reads 0. [5] dbgflag debug flag this bit is set and latched when debug mode is entered. writing a 1 to this bit clears the flag. [4:3] reserved 0 reserved always reads 0. [2] f1flag fault1 flag this bit is set and latched when fault1 is asserted. writing a 1 to this bit clears the flag. [1] c0flag comparator 0 flag this bit is set and latched when comparator is asserted. writing a 1 to this bit clears the flag. [0] fflag fault flag this bit is set and latched when the fault0 input is asserted. writing a 1 to this bit clears the flag. note : for this register, w1c means you must write one to clear the flag. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 130 pwm fault control register the pwm fault control (pwmfctl) register (see table 76 ), determines how the pwm recovers from a fault condition. settings in this register select automatic or software controlled pwm restart. table 76. pwm fault control register (pwmfctl) bits 7 6 5 4 3 2 1 0 field reserved dbgrst cmp1int cmp1rst cmpint cmprst fault0int fault0rst reset 0 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff_e388h bit position value (h) description [7] reserved 0 reserved [6] dbgrst 0 debugrestart automatic recovery. pwm resumes control of outputs when all fault sources have deasstered and a new pwm period begins. 1 s oftware controlled recovery. pwm resumes control of outputs only after all fault sources have deasserted and all fault flags are cleared and a pwm reload occurs. [5] cmp1int 0 comparator 1 interrupt interrupt on comparator assertion disabled. 1 interrupt on comparator assertion enabled. [4] cmp1rst 0 comparator 1 restart automatic recovery. pwm resumes control of outputs when all fault sources have deasstered. 1 s oftware controlled recovery. pwm resumes control of outputs only after all fault sources have deasserted and all fault flags are cleared and a pwm reload occurs. [3 cmp0int 0 comparator 0 interrupt interrupt on comparator 0 assertion disabled. 1 interrupt on comparator 0 assertion enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 131 pwm input sample register pwm pin value is sampled by reading this register. [2] cmp0rst 0 comparator 0 restart automatic recovery. pwm resumes control of outputs when all fault sources have deasstered. 1 s oftware controlled recovery . pwm resumes control of outputs only after all fault sources have deasserted and all fault flags are cleared and a pwm reload occurs. [1] fault0int 0 fault 0 interrupt interrupt on fault 0 pin assertion disabled. 1 interrupt on fault0 pin assertion enabled. [0] fault0rst 0 fault 0 restart automatic recovery. pwm resumes control of outputs when all fault sources have deasstered. 1 s oftware controlled recovery . pwm resumes control of outputs only after all fault sources have deasserted and all fault flags are cleared and a pwm reload occurs. table 77. pwm input sample register (pwmin) bits 7 6 5 4 3 2 1 0 field reserved fault in2l in2h in1l in1h in0l in0h reset 00000000 r/w r r/w r/w r/w r/w r/w r/w r/w addr ff_e386h bit position value (h) description [7] reserved must be 0. [6] fault 0 sample fault0 pin a low-level signal was read on the fault pin. 1 a high-level signal was read on the fault pin. bit position value (h) description www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 132 pwm output control register the pwm output control (pwmout) register enables modulator control of the six pwm output signals. output cont rol is enabled by the outctl bit in the pwmctl0 register. the pwm continues to operate but has no ef fect on the disabled pwm pins. if a fault condition is detected, all pwm outputs ar e forced to their selected off state. . current-sense sample and hold control registers the current-sense sample/hold control register defines the behavior of the dedicated current sense sample and hold inputs to th e adc from the operational amplifier. these input hold the current input va lue whenever all high-side outputs or all low-side outputs are in the on-state. the register bits cont rol which pwm outputs must be asserted to [5:0] in2l/in2h/ in1l/in1h/ in0l/in0h 0 sample pwm pins a low-level signal was read on the pins. 1 a high-level signal was read on the pins. table 78. pwm output control register (pwmout) bits 7 6 5 4 3 2 1 0 field reserved reserved out2l out2h out1l out1h out0l out0h reset 00000000 r/w r r r/w r/w r/w r/w r/w r/w addr ff_e387h bit position value (h) description [7,6] reserved must be 0. [5, 3, 1] out2l/ out1l/ out0l 0 pwm 2l/1l/0l output configuration pwm 2l/1l/0l output signal is enabled and controlled by pwm. 1 pwm 2l/1l/0l output signal is in low-side off-state. [4, 2, 0] out2h/ out1h/ out0h 0 pwm 2h/1h/0h output configuration pwm 2h/1h/0h output signal is enabled and controlled by pwm. 1 pwm 2h/1h/0h output signal is in high-side off-state. bit position value (h) description www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y multi-channel pwm timer zneo ? Z16F series product specification 133 activate the internal hold signal. disabling the hen, len, nhen, and nlen bits allows software control of the input sample/hold by writing the shpol bit. . table 79. current-sense sample and hold control register (csshr0 and csshr1) bits 7 6 5 4 3 2 1 0 field shpol hen nhen len nlen shpwm2 shpwm1 shpwm0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e38ah and ff_e38bh bit position value (h) description [7] shpol 0 sample hold polarity hold when terms are active. 1 hold when terms are not active. [6] hen 0 high side active enable ignore product of pwmh0, pwmh1, pwmh2 in sample/hold equation. 1 hold when pwmh0, pwmh1, pwmh2 are all active. [5] nhen 0 high side inactive enable ignore product of pwmh0 , pwmh1 , pwmh2 in sample/hold equation. 1 hold when are all active. [4] len 0 low side active enable ignore product of pwml0, pwml1, pwml2 in sample/hold equation. 1 hold when pwml0, pwml1, pwml2 are all active. [3] nlen 0 low side inactive enable ignore product of pwml0 , pwml1 , pwml2 in sample/hold equation. 1 hold when pwml0 , pwml1 , pwml2 are all active. [2] shpwm2 0 pwm channel2 sample/hold enable channel 2 terms are not used in sample/hold equation. 1 channel 2 terms are used in sample/hold equation. [1] shpwm1 0 pwm channel1 sample/hold equation channel 1 terms are not used in sample/hold equation. 1 channel 1 terms are used in sample/hold equation. [0] shpwm0 0 pwm channel0 sample/hold equation channel 0 terms are not used in sample/hold equation. 1 channel 0 terms are used in sample/hold equation. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 134 lin-uart the local interconnect network universal asynchronous receiver/transmitter (lin- uart) is a full-duplex communication channel capable of handling asynchronous data transfers in standard uart applications as well as providing lin protocol support. features of the lin-uart include: ? 8-bit asynchronous data transfer. ? selectable even and odd-par ity generation and checking. ? option of one or two stop bits. ? selectable multiprocessor (9-bit) mode with three configurable interrupt schemes. ? separate transmit and receive interrupts or dma requests. ? framing, parity, overrun, and break detection. ? 16-bit baud rate generator (brg), which functions as a general-purpose timer with interrupt. ? driver enable output for external bus transceivers. ? lin protocol support for both master and slave modes: ? break generation and detection. ? selectable slave autobaud. ? check tx versus rx data when sending. ? configurable digital noise filter on receive data line. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 135 architecture the lin-uart consists of three primary functional blocks: transmitter , receiver , and brg . the lin-uart?s transmitter and receiver function independently but use the same baud rate and data format. the basic uart operation is enhanced by the noise filter and irda blocks. figure 23 displays the lin-uart architecture. figure 23. lin-uart block diagram receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status registers register register register de with address compare baud rate generator irda noise filter rx irq tx irq rxdmareq txdmareq www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 136 operation data format for standard uart modes the lin-uart always transmits and receives data in an 8-bit data format with the first bit being least-significant bit. an even- or odd-pari ty bit or multiprocessor address/data bit is optionally added to the data stream. each char acter begins with an active low start bit and ends with either 1 or 2 active high stop bits. figure 24 and figure 25 displays the asynchronous data format empl oyed by the lin-uart without parity and with parity, respectively. figure 24. lin-uart asynchronous data format without parity figure 25. lin-uart asynchronous data format with parity transmitting data using the polled method follow the steps below to transmit da ta using the polled operating method: 1. write to the lin-uart baud rate high an d low byte registers to set the appropriate baud rate. 2. enable the lin-uart pin functions by config uring the associated gpio port pins for alternate function operation. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 startbit0bit1bit2bit3bit4bit5bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 137 3. if multiprocessor mode is required, wr ite to the lin-uart control 1 register to enable multiprocessor (9-bit) mode functions. (a) set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 4. write to the lin-uart control 0 register to: (a) set the transmit enable bit ( ten ) to enable the lin-uart for data transmission. (b) if parity is required and multiprocess or mode is not enabled, set the parity enable bit ( pen ) and select either even- or odd parity ( psel ). (c) set or clear the ctse bit to enable or disable control from the remote receiver using the cts pin. 5. check the tdre bit in the lin-uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if th is register is empty, continue to step 6. if the transmit data register is full (indicated by a 0), continue to monitor the tdre bit until the transmit data register beco mes available to receive new data. 6. if in multiprocessor mode, write the lin- uart control 1 register to select the outgoing address bit. (a) set the multiprocessor bit transmitter (mpb t) if sending an address byte; clear it if sending a data byte. 7. write the data byte to the lin-uart transmit data register. the transmitter automatically transfers the data to the tran smit shift register and transmits the data. 8. if multiprocessor mode is required an d multiprocessor mode is enabled, make any changes to the multiprocess or bit transmitter (mpbt) value. 9. to transmit additional bytes, return to step 4. transmitting data using interrupt-driven method the lin-uart transmitter interrupt indicates th e availability of the tr ansmit data register to accept new data for transmis sion. follow the steps below to configure the lin-uart for interrupt-driven data transmission: 1. write to the lin-uart baud rate high and low byte registers to set the appropriate baud rate. 2. enable the lin-uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the lin-uart transmitter interrupt and set the appropriate priority. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 138 5. if multiprocessor mode is required, wr ite to the lin-uart control 1 register to enable multiprocessor (9-bit) mode functions. (a) set the multiprocessor mode select (mpen) to enable multiprocessor mode. 6. write to the lin-uart control 0 register to: (a) set the transmit enable bit (ten) to enable the lin-uart for data transmission (b) enable parity, if multiprocessor mode is not enabled, and select either even or odd parity. (c) set or clear the ctse bit to enable or disable control fro m the remote receiver through the cts pin. 7. execute an ei instruction to enable interrupts. the lin-uart is now configur ed for interrupt-driven data transmission. as the lin- uart transmit data register is empty, an interrupt is ge nerated immediately. when the lin-uart transmit interrupt is detected and there is transmit data ready to send, the associated interrupt service rouisr performs the following: 1. if operating in multiprocessor mode, wr ite the lin-uart control 1 register to select the outgoing address bit: (a) set the multiprocessor bit transmitter (mpb t) if sending an address byte; clear it if sending a data byte. 2. write the data byte to the lin-uart transmit data register. the transmitter automatically transfers the data to the tran smit shift register and transmits the data. 3. execute the iret instruction to return from the inte rrupt service routine and waits for the transmit data register to again become empty. if a transmit interrupt occurs and there is no transmit data ready to send, the interrupt service routine executes the iret instruction. when the application does have data to transmit, software sets the appr opriate interrupt requ est bit in the interrupt controller to initiate a new transmit interrupt. another alternative would be fo r software to write the data to the transmit data register instead of invoking the isr. receiving data using polled method follow the steps below to configure th e lin-uart for polled data reception: 1. write to the lin-uart baud rate high an d low byte registers to set the appropriate baud rate. 2. enable the lin-uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the lin-uart control 1 regi ster to enable multiprocessor mode functions. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 139 4. write to the lin-uart control 0 register to: (a) set the receive enable bit (ren) to enable the lin-uart for data reception (b) enable parity, if multiprocessor mode is not enabled, and select either even or odd parity. 5. check the rda bit in the lin-uart status 0 register to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to st ep 6. if the receive data register is empty (indicated by 0), continue to monitor the rda bit awaiting reception of the valid data. 6. read data from the lin-uart recei ve data register. if operating in multiprocessor (9-bit) mode, further ac tions are required depending on the multiprocessor mode bits mpmd [1:0]. 7. return to step 5 to receive additional data. receiving data using the interrupt-driven method the lin-uart receiver interrupt indicates the availability of new data (as well as error conditions). follow the steps below to confi gure the lin-uart receiver for interrupt- driven operation: 1. write to the lin-uart baud rate high an d low byte registers to set the appropriate baud rate. 2. enable the lin-uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the lin-uart receiver interrupt and set the appropriate priority. 5. clear the lin-uart receiver interrupt in the applicable interrupt request register. 6. write to the lin-uart control 1 regi ster to enable multiprocessor (9-bit) mode functions: (a) set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. (b) set the multiprocessor mode bits, mpmd[1:0], to select the appropriate address matching scheme. (c) configure the lin-uart to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for zneo devices without a dma block). 7. write the device address to the address compare register (aut omatic multiprocessor modes only). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 140 8. write to the lin-uart control 0 register to: (a) set the receive enable bit ( ren ) to enable the lin-uart for data reception (b) enable parity, if multiprocessor mo de is not enabled, and select either even- or odd-parity. 9. execute an ei instruction to enable interrupts. the lin-uart is now configur ed for interrupt-driven data reception. when the lin- uart receiver interrupt is detected, the associated isr performs the following: 1. check the lin-uart status 0 register to determine whether the source of the interrupt is error, break, or received data. 2. if the interrupt was due to data availabl e, read the data from the lin-uart receive data register. if operating in multiproc essor (9-bit) mode, further actions are required depending on the multiprocessor mode bits mpmd[1:0] . 3. execute the iret instruction to return from the isr and await more data. clear to send operation the clear to send (cts) pin, if enabled by the ctse bit of the lin-uart control 0 register, performs flow control on the outgoing transmit data stream. the cts input pin is sampled one system clock before beginning any new character transmission. to delay transmission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data tr ansmission begins. for multiple character transmissions, this operation is typically pe rformed during the stop bit transmission. if cts deasserts in the middle of a character transmission, the current character is sent completely. external driver enable the lin-uart provides a driver enable (de) signal for off-chip bus transceivers. this feature reduces the software overhead associ ated with using a gpio pin to control the transceiver when communicating on a multi-transceiver bus such as rs-485. driver enable is a programmable polarity si gnal which envelopes th e entire transmitted data frame including parity and stop bits as illustrated in figure 26 on page 141. the de signal asserts when a byte is written to the lin-uart transmit data register. the de signal asserts at least one bit period and no greater than two bit periods before the start bit is transmitted. this allows a set-up time to enab le the transceiver. the de signal deasserts one system clock period after the last stop bit is transmitted. this one system clock delay allows both time for data to clear the transceive r before disabling it, as well as the ability to determine if another character follows the curren t character. in the ev ent of back to back characters (new data must be written to th e transmit data register before the previous character is completely transmitted) the de si gnal is not deasserted between characters. the depol bit in the lin-uart control regist er 1 sets the polarity of the de signal. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 141 figure 26. lin-uart driver enable signal timing (shown with 1 stop bit and parity) the de to start bit setup time is calculated as follows: lin-uart special modes the special modes of the lin-uart: ? multiprocessor mode ? lin mode the lin-uart has a common control register (control 0), which has a unique register address and several mode specific control re gisters (multiprocessor control, noise filter control, and lin control) which share a commo n register address (control 1). when the control 1 address is read or written, the mode select ( msel[2:0]) field of the mode select and status register determines which physical re gister is accessed. similarly, there are mode specific status registers, one of which is returned when the status 0 register is read, depending on the msel field. multiprocessor (9-bit) mode the lin-uart features a multiprocessor (9-bit) mode which uses an extra (9 th ) bit for selective communication wh en a number of processors share a common uart bus. in multiprocessor mode (also referred to as 9-bit mo de), the multiprocessor bit ( mp ) is transmitted immediately following the 8 bits of data and immediately preceding the stop bit(s) as illustrated in figure 27 on page 142. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de 1 baud rate (hz) ------------------- ------------------ ?? ?? de to start bit setup time (s) 2 baud rate (hz) ------------------- ------------------ ?? ?? ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 142 the character format is given below: figure 27. lin-uart asynchronous multiprocessor mode data format in multiprocessor (9-bit) mode, the parity bit location (9th bit) becomes the multiprocessor control bit. the lin-uart control 1 and status 1 registers provide multiprocessor (9-bit) mode control and stat us information. if an automatic address matching scheme is enabled, the lin-uart address compare register holds the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is enabled, the lin-uart processes only frames addressed to it. you can determine whether a fr ame of data is addressed to the lin-uart is made in hardware, software or a combinatio n of the two, depending on the multiprocessor configuration bits. in general, the address comp are feature reduces the load on the cpu because it does not need to access the lin-uart when it receives data directed to other devices on the multi-node network. the following 3 multiprocessor modes are available in the hardware: 1. interrupt on all address bytes. 2. interrupt on matched address bytes and correctly framed data bytes. 3. interrupt only on corre ctly framed data bytes. these modes are selected with mpmd[1:0] in the lin-uart control 1 register. for all multiprocessor modes, bit mpen of the lin-uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0] . in this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. the isr checks the address byte which trigge red the interrupt. if it matches the lin-uart address, the software clears mpmd[0] . at this point, each new incoming byte interrupts the cpu. the software determines the end of the fr ame and checks for it by reading the mprx bit of the lin-uart status 1 register for each incoming byte. if mprx =1 , a new frame has begun. if the address of this new frame is differ ent from the lin-uart?s address, then mpmd[0] must be set to 1 by software, causing the lin- uart interrupts to go inactive until the next startbit0bit1bit2bit3bit4bit5bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 143 address byte. if the new frame?s address matches the lin-uart?s, then the data in the new frame is processed. the second scheme is enabled by setting mpmd[1:0] to 10b and writing the lin-uart?s address into the lin-uart address compar e register. this mode introduces more hardware control, interrupting only on fr ames which match the address of lin-uart. when an incoming address byte does not match the address of lin-uart, it is ignored. all successive data bytes in this frame are also ignored. when a matching address byte occurs, an interrupt is issued and further interrupts occur on each successive data byte. the first data byte in the frame has newfrm=1 in the lin-uart status 1 register. when the next address byte occurs, the hardware compares it to the address of lin-uart. if there is a match, the interrupt occurs and the newfrm bi t is set for the first byte of the new frame. if there is no match, the lin-uart ignores all incoming bytes until the next address match. the third scheme is enabled by setting mpmd[1:0] to 11b and by writing the address of lin-uart into the lin-uart address compare register. this mode is identical to the second scheme, except that there are no interrupts on address bytes. the first data byte of each frame remains accompanied by a newfrm assertion. lin protocol mode the lin protocol as supported by the lin-uart module is defined in revision 2.0 of the lin specification package. the lin protocol sp ecification covers all aspects of transferring information between lin master and slave de vices using message frames including error detection and recovery, sleep mode, and wake up from sleep mode. the lin-uart hardware in lin mode provides character tran sfers to support the lin protocol including break transmission and detection, wake-u p transmission and detection, and slave autobauding. part of the error detection of the lin protocol is for both master and slave devices to monitor their receive data when transmitting. if the rece ive and transmit data streams do not match, the lin-uart asserts the ple bit (physical layer error bit in status0 register). the message frame timeo ut aspect of the protocol is left to software, requiring the use of an additional general purpose timer. the lin mode of th e lin-uart does not provide any hardware support for computing/veri fying the checksum field or to verify the contents of the identifier field. these fields ar e treated as data and ar e not interpreted by the hardware. the lin bus contains a single master and one or more slaves. the lin master is responsible for transmitting the message frame h eader which consists of the break, synch, and identifier fields. eith er the master or one of the slaves transmits the associated response section of the message, which consists of data characters followed by a checksum character. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 144 in lin mode, the interrupts defined for no rmal uart operation still apply with the following changes: ? parity error (pe bit in status0 register) is redefined as the physi cal layer error (ple) bit. the ple bit indicates that receive data does not matc h transmit data when the lin- uart is transmitting. this applies to both master and slave operating modes. ? the break detect interrupt ( brkd bit in status0 register) indicates when a break is detected by the slave (break condition for at least 11 bit times). software uses this interrupt to start a timer checking for mess age frame time-out. the duration of the break is read in the rxbreaklength[3:0] field of the mode status register. ? the break detect interrupt ( brkd bit in status0 register) indicates when a wake-up message has been received if the lin-uart is in linsleep state. ? in lin slave mode, if the brg counter overflows while measuring the autobaud period ( start bit to beginning of bit 7 of autobaud character) an overrun error is indicated ( oe bit in the status0 regist er). in this case, software sets the linstate field back to 10b , where the slave ignores the current message and waits for the next break signal. the baud reload high and low registers are not updated by hardware if this autobaud erro r occurs. the oe bit is also set if a data overrun error occurs. lin system clock requirements the lin master provides the timing reference for the lin network and is required to have a clock source with a tolerance of 0.5%. a slave with autobaud capability is required to have a baud clock matching the master oscillator within 14%. the slave nodes autobaud to lock onto the master timing reference with an accuracy of 2%. if a slave does not contain autobaud capability, it must include a baud clock which deviates from the masters by no more than 1.5%. these accuracy requir ements must include effects such as voltage and temperature drift during operation. before sending or receiving messages, the baud reload high/low registers must be initialized. unlike standard uart modes, the baud reload high/low registers must be loaded with the baud in terval rather than 1/16 of the baud interval. in order to autobaud with the required accuracy, the lin slave system clock must be at least 100 times the baud rate. lin mode initialization and operation the lin protocol mode is selected by setting either the lin master ( lmst ) or lin slave ( lslv ), and optionally (for lin slave) the autobaud enable ( aben ) bits in the lin control register. to access the lin control register, the mode select (msel) field of the lin- uart mode select/status register must be 010b . the lin-uart control0 register must be initialized with ten = 1, ren = 1, all other bits = 0. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 145 in addition to the lmst, lslv, and aben bits in the lin control register, a linstate[1:0] field exists that defines the current state of th e lin logic. this field is initially set by the software. in the lin slave mode, the linstate field is updated by hardware as the slave moves through the wait for break, autobaud, and active states. the noise filter is also required to be enabled and configured when interfacing to a lin bus. lin master mode operation lin master mode is selected by setting th e bits lmst = 1, lslv = 0, aben = 0, linstate[1:0] = 11b. if the lin bus protocol indicates the bus is required go into the lin sleep state, the linstate[1 :0] bits must be set = 00b by the software. the break is the first part of the message fram e transmitted by the master, consisting of at least 13 bit periods of logical zero on the lin bus. during initialization of the lin master, the duration (in bit times) of the break is written to the txbreaklength field of the lin control register. the transmission of the break is performed by setting the sbrk bit in the control 0 register. the lin-uart starts the break once the sbrk bit is set and any character transmission currently underway has completed. the sbrk bit is deasserted by hardware once the break is completed. the synch character is transmitted by writing a 55h to the transmit data register ( tdre must be 1 before writing). the synch charac ter is not transmitted by the hardware until after the break is complete. the identifier character is transmitted by writ ing the appropriate value to the transmit data register ( tdre must be 1 before writing). if the master is sending the response portion of the message, these data and checksum characters are written to the transmit da ta register when the tdre bit asserts. if the transmit data register is written afte r tdre asserts, but before txe asserts, the hardware inserts one or two stop bits between each character as determined by the stop bit in the control0 register. additional idle tim e occurs between characters if txe asserts before the next character is written. lin sleep mode while the lin bus is in the sleep state, the cpu is in either low power stop mode, in halt mode, or in normal operational state. any device on the lin bus issues a wake-up message (transmit an 80h character) if it needs the master to initiate a lin message frame. following the wake-up messag e, the master wakes up and initiates a new message. if the cpu is in stop mode, the lin-uart is not active and the wake-up message must be detected by a gpio edge detect stop mode recovery. the duration of the stop mode recovery sequence may preclude making an accurate measurement of the wake-up message duration. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 146 if the cpu is in halt or operational mo de, the lin-uart (if enabled) times the duration of the wake-up and prov ides an interrupt following the end of the break sequence if the duration is 4 bit times. the total duration of the wake-up message in bit times is obtained by reading the rxbreaklength field in the mode status register. after a wake-up message is detected, the lin-uart is placed (b y software) into either lin master or lin slave wait for break states as appropriate. if the break duration ex ceeds fifteen bit times, the rxbreaklength field contains the value fh . lin sleep state is selected by software setting linstate[1:0] = 00 . the decision to move from an active state to sleep state is ba sed on the lin messages as interpreted by the software. lin slave operation lin slave mode is select ed by setting the bits lmst = 0 , lslv = 1 , aben = 1 or 0 and linstate[1:0] = 01b (wait for break state). the lin slave detects the start of a new message by the break which appears to the slav e as a break of at least 11 bit times in duration. the lin-uart detects the break and generates an interrupt to the cpu. the duration of the break is observable in the rxbreaklength field of the mode status register. a break of less than 11 bit times in duration does not generate a break interrupt when the lin-uart is in ?wait for break? state. if the break duration exceeds 15 bit times, the rxbreaklength field contains the value fh . following the break the lin-uart hardware automa tically transits to the autobaud state, where it autobauds by timing the duration of the first 8 bit times of the synch character as defined in the standard. at the end of the au tobaud period, the duration measured by the brg counter (auto baud period divided by 8) is automatica lly transferred to the baud reload high and low registers if the aben bit of the lin control register is set. if the brg counter overflows before reaching the start of bit 7 in the autobaud sequence the autobaud overrun error interrupt occurs, the oe bit in the status0 register is set and the baud reload registers are not updated. to autobaud within 2% of the master?s baud rate, the slave system clock must be minimum 100 times the baud rate. to avoid an autobaud overrun error, the system clock must not be greater than 2 19 times the baud rate (16 bit counter following 3- bit prescaler when counting the 8 b it times of the autobaud sequence). following the synch character, the lin-uart ha rdware transits to the active state, where the identifier character is received and the ch aracters of the response section of the message are sent or received. the slave remains in the active state until a break is received or the software forces a state change. when it is in active state (autobaud has completed), a break of 10 or more bit times is recognized and a transition to the autobaud state is caused. lin-uart interrupts the lin-uart features separate interrupts for the transmitter and receiver. in addition, when the lin-uart primary functionality is disabled, the brg also functions as a basic timer with interrupt capability. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 147 transmitter interrupts the transmitter generates a sing le interrupt when the transm it data register empty bit ( tdre ) is set to 1. this indicates that the tr ansmitter is ready to accept new data for transmission. the tdre interrupt occurs when the transmitter is initially enabled and after the transmit shift register has shifted the first bit of a character out. at this point, the transmit data register is written with the next character to send. this provides 7 bit periods of latency to load the transmit data register before the transmit shift register completes shifting the current character. writing to the lin-uart transmit data register clears the tdre bit to 0. receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte is received and is available in the lin-uart receive data register. this interrupt is disabled independent of the ot her receiver interrupt sources using the rdairq bit (this feature is useful in devices , which support dma). the received data interrupt occurs after the receive character is placed in the receive data register. to avoid an overrun error, the so ftware responds to this r eceived data available condition before the next character is completely received. in multiprocessor mode ( mpen = 1 ), the receive data interrupts are dependent on the multiprocessor configuration a nd the most recent address byte. ? a break is received. ? a receive data overrun or lin slave autobaud overrun error is detected. ? a data framing error is detected. ? a parity error is detected (phy sical layer error in lin mode). lin-uart overrun errors when an overrun error condition occurs, the lin-uart prevents overwriting of the valid data currently in the receive data register. the break detect and overrun status bits are not displayed until the valid data is read. when the valid data is read, the oe bit of th e status0 register is updated to indicate the overrun condition (and break detect, if applicab le). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error occurred, this byte may not contain valid data and must be ignored. the brkd bit indicates if the overrun is caused due to a break condition on the line. after read ing the status byte indicating an overrun error, the receive data re gister must be read again to clear the error bits in the lin-uart status0 register. in lin mode, an overrun error is signaled for receive data overruns as described above and in the lin slave, if the brg counter ove rflows during the autobaud sequence (the atb bit will also be set in this case). there is no data associated with the autobaud overflow note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 148 interrupt, however the receive data register must be read to clear the oe bit. in this case software must write 10b to the linstate field, forcing the lin slave back to wait for break state. lin-uart data and error handling procedure figure 28 displays the recommended procedure fo r use in lin-uart receiver interrupt service routines. baud rate generator interrupts if the brgctl bit of the multiprocessor control register (lin-uart control 1 register with msel = 000b) register is set, and the ren bit of the control0 register is 0, the lin- uart receiver interrupt asserts when the li n-uart baud rate generator reloads. this figure 28. lin-uart receiver in terrupt service routine flow receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 149 action allows the brg to function as an additional counter if the lin-uart receiver functionality is not employed. the transmitter is enabled in this mode. lin-uart dma interface the dma engine is configured to move uart transmit and/or receive data. this reduces processor overhead, especially when moving blocks of data. the dma interface on the lin-uart consists of the txdmareq and rxdmareq outputs, and the txdmaack and rxdmaack inputs. any of the dma channels ar e configured to process the uart dma requests. if transmit data is to be moved by the dma, th e transmit interrupt must be disabled in the interrupt controller. if receive data is to be moved by the dma, the rdairq bit in the lin-uart control 1 register must be set. this disables receive data interrupts when still enabling error interrupts. the rece ive interrupt must be enabled in the interrupt controller to process error cond ition interrupts. lin-uart baud rate generator the lin-uart baud rate generator creates a lower frequency baud rate clock for data transmission. the input to the brg is the syst em clock. the lin-uart baud rate high and low byte registers combine to create a 16-bit baud rate divisor value ( brg[15:0] ) which sets the data transmission ra te (baud rate) of the lin-uart . the lin-uart data rate is calculated using the following equation for normal uart operation: the lin-uart data rate is calculated usin g the following equation for lin mode uart operation: when the lin-uart is disabled, the brg functi ons as a basic 16-bit timer with interrupt on timeout. follow the steps below to config ure brg as a timer with interrupt on timeout: 1. disable the lin-uart receiver by clearing the ren bit in the lin-uart control 0 register to 0 (ten bit is asserted, transmit activity may occur). 2. load the appropriate 16-bit count value into the lin-uart baud rate high and low byte registers. 3. enable the brg timer functio n and associated interrupt by setting the brgctl bit in the lin-uart control1 register to 1. enable the uart receiv e interrupt in the interrupt controller. uart data rate (bps) system clock frequency (hz) 16 uart baud rate divisor value --------------------- --------------------- --------------------- ------------------ ------------- = uart data rate (bps) system clock frequency (hz) uart baud rate divisor value ------------------ ---------------------- --------------------- -------------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 150 when configured as a general purpose timer, th e brg interrupt interval is calculated using the following equation: noise filter a noise filter circuit is included, which filters noise on a digital input signal such as uart receive data before the data is sampled by the block. this is a requirement for protocols with a noisy environment. the noise filter includes following features: ? synchronizes the receive input data to the system clock. ? noise filter enable ( nfen) input selects whether the no ise filter is bypassed ( nfen = 0) or included ( nfen = 1) in the receive data path. ? noise filter control ( nfctl[2:0]) input selects the width of the up/down saturating counter digital filter. the available widths range is from 4 to11 bits. ? the digital filter ou tput has hysteresis. ? provides an active low saturated state output ( filtsatb ), used to indicate presence of noise. architecture figure 29 displays how the noise filter is integrat ed with the lin-uart for use on a lin network. uart brg interrupt interval (s ) system clock period (s) brg[15:0] = rxd txd noise filter lin-uart rxd txd system clock lin transceiver rxd txd gpio nfen, nfctl lin bus filtsatb www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 151 figure 29. noise filter system block diagram operation figure 30 on page 152 displays the operation of th e noise filter with and without noise. the noise filter in this example is a 2-bit up/down counter, which saturates at 00b and 11b . a 2- bit counter is shown for convenience, the opera tion of wider counters is similar. the output of the filter switches from 1 to 0 when the counter counts down from 01b to 00b and switches from 0 to 1 when the counter counts up from 10b to 11b . the noise filter delays the received data by three system clock cycles. the filtsatb signal is checked when the filtered rxd is sampled in the center of the bit time. the presence of noise ( filtsatb = 1 at center of bit time) does not mean the sampled data is incorrect, just that the filter is not in its sa turated state of all 1?s or all 0?s. if filtsatb = 1 when rxd is sampled during a receive character, the ne bit in the modestatus[4:0] field is set. an indication of th e level of noise in the network is obtained by observing this bit. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 152 figure 30. noise filter operation lin-uart control register definitions the lin-uart control registers support the lin-uart, the associated infrared encoder/ decoder and the noise filter. for detailed information on the infrared operation, see infrared encoder/decoder on page 171. 16x sample input baud period data bit = 0 data bit = 1 rxd (ideal) clock data bit=0 data bit=1 input rxd (noisy) 3 3 2 1 0 0 0 0 0 0 1 2 1 0 0 0 0 0 1 0 1 2 3 3 3 3 2 3 3 3 3 3 3 3 output rxd noise filter up/dn cntr noise filter filtsatb output uart sample point noise filter up/dn cntr 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 output rxd noise filter nominal filter delay clean rxd example noise rxd example www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 153 lin-uart transmit data register data bytes written to the lin-ua rt transmit data register (see table 80 ) are shifted out on the txd pin. the write-only lin-uart transmit data register shares a register file address with the read-only lin-uart receive data register. txd?transmit data lin-uart transmitter data byte to be shifted out through the txd pin. lin-uart receive data register data bytes received through th e rxd pin are stored in the lin-uart receive data register ( table 81 ). the read-only lin-uart receive data register shares a register file address with the write-only lin-uart transmit data register. rxd?receive data lin-uart receiver data byte from the rxd pin table 80. lin-uart transmit data register (uxtxd) bits 7 6 5 4 3 2 1 0 field txd reset x r/w w addr ff-e200h, ff-e210h table 81. lin-uart receive data register (uxrxd) bits 7 6 5 4 3 2 1 0 field rxd reset x r/w r addr ff-e200h, ff-e210h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 154 lin-uart status 0 register the lin-uart status 0 register identifies the current lin-uart operating configuration and status. table 82 below describes the status 0 register for standard uart mode. table 83 on page 155 describes the status 0 register for lin mode. rda?receive data available this bit indicates that the lin-uart receive data register has received data. reading the lin-uart receive data re gister clears this bit. 0 = the lin-uart receive data register is empty. 1 = there is a byte in the lin-uart receive data register. pe?parity error this bit indicates that a parity error has occurred. reading the receive data register clears this bit. 0 = no parity error occurred. 1 = a parity error occurred. oe?overrun error this bit indicates that an overrun error has oc curred. an overrun occu rs when new data is received and the receive data register has not been read. reading the receive data register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. fe?framing error this bit indicates that a framing error (no stop bit following data reception) is detected. reading the receive data re gister clears this bit. 0 = no framing error occurred. 1 = a framing error occurred. brkd?break detect this bit indicates that a break has occurred. if the data bits, parity/multiprocessor bit, and stop bit(s) are all zeros then this bit is set to 1. reading the receive data register clears this bit. table 82. lin-uart status 0 register ? standard uart mode (uxstat0) bits 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 000001 1 x r/w rrrrrr r r addr ff-e201h, ff-e211h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 155 0 = no break occurred. 1 = a break occurred. tdre?transmitter data register empty this bit indicates that the tr ansmit data register is empt y and ready for additional data. writing to the transmit data register resets this bit. 0 = do not write to the transmit data register. 1 = the transmit data register is ready to receive an additional byt e to be transmitted. txe?transmitter empty this bit indicates that the tran smit shift register is empty and character transmission is finished. 0 = data is currently transmitting. 1 = transmission is complete. cts? cts signal when this bit is read it returns the cts signal level. if lben = 1 , the cts input signal is replaced by the internal receive data availabl e signal to provide flow control in loopback mode. cts only affects transmission if the ctse bit = 1. rda?receive data available this bit indicates that the recei ve data register has received data. reading the receive data register clears this bit. 0 = the receive data register is empty. 1 = there is a byte in the receive data register. ple?physical layer error this bit indicates that transmit and receive data do not match when a lin slave or master is transmitting. this is caused by a fault in the physical layer or multiple devices driving the bus simultaneously. reading the status 0 register or the receive data register clears this bit. 0 = transmit and receive data match. 1 = transmit and receive data do not match. table 83. lin-uart status 0 register ? lin mode (uxstat0) bits 7 6 5 4 3 2 1 0 field rda ple oe fe brkd tdre txe atb reset 000001 1 0 r/w rrrrrr r r addr ff-e201h, ff-e211h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 156 oe?receive data and autobaud overrun error this bit is set just as in no rmal uart operation if a receive data overrun error occurs. this bit is also set during lin slave autobaud if the brg counter overflows before the end of the autobaud sequence, indicating that the receive activity was not an autobaud character or the master baud rate is too slow. the atb stat us bit will also be set in this case. this bit is cleared by reading the receive data register. 0 = no autobaud or data overrun error occurred. 1 = an autobaud or data overrun error occurred. fe?framing error this bit indicates that a framing error (no stop bit following data reception) is detected. reading the receive data re gister clears this bit. 0 = no framing error occurred. 1 = a framing error occurred. brkd?break detect this bit is set in lin mode if (a) in linsl eep state and a break of at least 4 bit times occurred (wake-up event) or (b) in slave wait break state and a break of at least 11 bit times occurred (break event), or (c) in slave active state and a break of at least 10 bit times occurs. reading the status 0 register or the receive data register clears this bit. 0 = no lin break occurred. 1 = a lin break occurred. tdre?transmitter data register empty this bit indicates that the tr ansmit data register is empt y and ready for additional data. writing to the transmit data register resets this bit. 0 = do not write to the transmit data register. 1 = the transmit data register is ready to receive an additional byt e to be transmitted. txe?transmitter empty this bit indicates that the tran smit shift register is empty and character transmission is finished. 0 = data is currently transmitting. 1 = transmission is complete. atb?lin slave autobaud complete this bit is set in lin slave mode when an autobaud charact er is received. if the abien bit is set in the lin control register then a rece ive interrupt is generated when this bit is set. reading the status 0 register clears this bi t. this bit will be 0 in lin master mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 157 lin-uart mode select and status register this register contains mode select and status bits. msel?mode select this r/w field determines which control register is accessed when performing a write or read to the uart control 1 register address. this field also determines which status is returned in the mode status field when reading this register. 000 = multiprocessor and normal uart control/status 001 = noise filter control/status 010 = lin protocol control/status 011?110: reserved 111 = lin-uart hardware revision (allows hardware revision to be read in the mode status field) mode status ?this read-only field returns status corresponding to the mode selected by msel as follows: 000: multiprocessor and normal uart mode status = { ne , 0, 0, newfrm, mprx } 001: noise filter status = { ne , 0,0,0,0} 010: lin mode status = { ne, rxbreaklength[3:0 ]} 011?110: reserved = {0, 0, 0, 0, 0} 111: lin-uart hardware revision multiprocessor mode status field (msel = 000b) ne?noise event this bit is asserted if digital noise is detect ed on the receive data line when the data is sampled (center of bit time). if this bit is se t, it does not mean that the receive data is corrupted (in extreme cases), just that one or more of the noise filter data samples near the center of the bit time did not match the average data value. newfrm ?status bit denoting the start of a new frame. reading the lin-uart receive data register resets this bit to 0. table 84. lin-uart mode select and status register (uxmdstat) bits 7 6 5 4 3 2 1 0 field msel mode status reset 000000 0 0 r/w r/w r/w r/w r r r r r addr ff-e204h, ff-e214h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 158 0 = the current byte is not the first data byte of a new frame. 1 = the current byte is the fi rst data byte of a new frame. mprx?multiprocessor receive returns the value of the last multiprocess or bit received. reading from the lin-uart receive data register resets this bit to 0. digital noise filter mode status field (msel = 001b) ne?noise event this bit is asserted if digital noise is detect ed on the receive data line while the data is sampled (center of bit time). if this bit is se t, it does not mean that the receive data is corrupted (in extreme cases), just that one or more of the noise filter data samples near the center of the bit time did not match the average data value. lin mode status field (msel = 010b) ne?noise event this bit is asserted if some no ise level is detected on the recei ve data line wh en the data is sampled (center of bit time). if this bit is set, it does not indicate that the receive data is corrupt (in extreme cases), just that one or mo re of the 16x data samples near the center of the bit time did not match the average data value. rxbreaklength ?lin mode received break length. th is field is read following a break (lin wake-up or break) so software determine s the measured duration of the break. if the break exceeds 15 bit times the value saturates at 1111b . hardware revision mode status field (msel = 111b) this field indicates th e hardware revision of the lin-uart block. 00_xxx lin uart hardware rev 01_xxx reserved 10_xxx reserved 11_xxx reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 159 lin-uart control 0 register the lin-uart control 0 register (see table 85 ) configures the basic properties of the lin-uart?s transmit an d receive operations. ten?transmit enable this bit enables or di sables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled. 1 = transmitter enabled. ren?receive enable this bit enables or disables the receiver. 0 = receiver disabled. 1 = receiver enabled. ctse?cts enable 0 = the cts signal has no effect on the transmitter. 1 = the lin-uart recognizes the cts signal as an enable control for the transmitter. pen?parity enable this bit enables or disables parity. ev en or odd is determined by the psel bit. 0 = parity is disabled. this bit is overridden by the mpen bit. 1 = the transmitter sends data with an additional pari ty bit and the receiver receives an additional parity bit. psel?parity select 0 = even parity is transmitted an d expected on all received data. 1 = odd parity is transmitted and expected on all received data. sbrk?send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so ensure that the tran smitter has finished sending data before setting this bit. in standard uart mode, the duration of the break is determined by how long software leaves this bit asserted. also the duration of any required stop bits following the break must be timed by software before writing a new byte to be transmitted to the transmit data register. in lin mode, the master sends a break character by asserting sbrk . the duration of the table 85. lin-uart control 0 register (uxctl0) bits 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff-e202h, ff-e212h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 160 break is timed by hardware, and the sbrk bit is deasserted by hardware when the break is completed. the duration of the break is determined by the txbreaklength field of the lin control register. one or two stop bits are auto matically provided by the hardware in lin mode as defined by the stop bit. 0 = no break is sent. 1 = the output of the transmitter is 0. stop?stop bit select 0 = the transmitter sends one stop bit. 1 = the transmitter sends two stop bits. lben?loop back enable 0 = normal operation. 1 = all transmitted data is looped back to the receiver within the irda module. mpmd[1:0]?multiprocessor mode if multiprocessor (9-bit) mode is enabled, 00 = the lin-uart generates an interrupt request on al l received bytes (data and address). 01 = the lin-uart generates an interrupt request only on received address bytes. 10 = the lin-uart generates an interrupt requ est when a received address byte matches the value stored in the address compare register and on all successive data bytes until an lin-uart control 1 registers multiple registers (see table 86 through table 88 ) are accessible by a single bus address. the register selected is determined by the mode select ( msel ) field. these registers provide additional control over the lin-uart operation. multiprocessor control regist er (lin-uart control 1 register with msel = 000b) when msel = 000b , this register provides control for uart multiprocessor mode, irda mode, baud rate timer mode as well as other features which applies to multiple modes. table 86. multiprocessor control register (uxctl1 with msel = 000b) bits 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff-e203h, ff-e213h with msel = 000b www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 161 address mismatch occurs. 11 = the lin-uart generates an in terrupt request on all received data bytes for which the most recent address byte matched the value in the address compare register. mpen?multiprocessor (9-bit) enable this bit is used to enable multiproce ssor (9-bit) mode. 0 = disable multiprocessor (9-bit) mode. 1 = enable multiprocessor (9-bit) mode. mpbt?multiprocessor bit transmit this bit is applicable only when mu ltiprocessor (9-bit) mode is enabled. 0 = send 0 in the multiprocessor bit location of the data stream (9th bit). 1 = send 1 in the multiprocessor bit location of the data stream (9th bit). depol?driver enable polarity 0 = de signal is active high. 1 = de signal is active low. brgctl?baud rate generator control this bit causes different lin-uart beha vior depending on whether the lin-uart receiver is enabled ( ren = 1 in the lin-uart control 0 register). when the lin-uart receiver is not enabled, this bit determines whether the baud rate generator issues interrupts. 0 = brg is disabled. reads from the baud rate high and low byte registers return the brg reload value. 1 = brg is enabled and counting. the brg generates a receive interrupt when it counts down to 0. reads from the baud rate high and low byte registers return the current brg count value. when the lin-uart receiver is enabled, this bit allows reads from th e baud rate registers to return the brg count value instead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and low byte registers return the current brg count value. unlike the timers, there is no mechanism to latch the high byte when the low byte is read. rdairq ?receive data interrupt enable 0 = received data and receiver errors generates an inte rrupt request to the interrupt controller. 1 = received data does not genera te an interrupt request to the in terrupt controller. only receiver errors generate an interrupt request. iren?infrared enco der/decoder enable 0 = infrared encoder/decoder is disabled. lin-uart operates normally. 1 = infrared encoder/decoder is enabled. the lin-uar t transmits and receives data through the infrared encoder/decoder. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 162 noise filter control register (lin-uart control1 register with msel = 001b). when msel = 001b , this register provides control for the digital noise filter. table 87. noise filter control register (uxctl1 with msel = 001b) nfen?noise filter enable 0 = noise filter is disabled. 1 = noise filter is enabled. receive data is preprocessed by the noise filter. nfctl?noise filter control this field controls the delay and noise rejectio n characteristics of the noise filter. the wider the counter the more delay that is introduced by the filter and the wider the noise event that is filtered. 000 = 4-bit up/down counter 001 = 5-bit up/down counter 010 = 6-bit up/down counter 011 = 7-bit up/down counter 100 = 8-bit up/down counter 101 = 9-bit up/down counter 110 = 10-bit up/down counter 111 = 11-bit up/down counter lin control register (lin-uart control1 register with msel = 010b) when msel = 010b , this register provides control for lin mode of operation. table 88. lin control register (uxctl1 with msel = 010b) bits 7 6 5 4 3 2 1 0 field nfen nfctl reserved reset 000000 0 0 r/w r/w r/w r/w r/w r r r r addr ff-e203h, ff-e213h with msel = 001b bits 7 6 5 4 3 2 1 0 field lmst lslv aben abien linstat e[1:0] txbreaklength reset 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff-e203h, ff-e213h with msel = 010b www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 163 lmst?lin master mode 0 = lin master mode not selected. 1 = lin master mode selected (if mpen, pen, lslv = 0) lslv?lin slave mode 0 = lin slave mode not selected. 1 = lin slave mode selected (if mpen, pen, lmst = 0) aben?autobaud enable 0 = autobaud not enabled. 1 = autobaud enabled if in lin slave mode. abien?autobaud interrupt enable 0 = interrupt following autobaud does not occur. 1 = interrupt following autobaud enabled if in lin slave mode. when the autobaud character is received, a receive interrupt is generated and the atb bit is set in the status0 register. linstate[1:0]?lin state machine the linstate is controlled by both hardware and software. software fo rce a state change at any time if necessary. in normal operation, so ftware moves the state in and out of sleep state. for a lin slave, software changes the st ate from sleep to wait for break after which hardware cycles through the wait for break, autobaud and active states. software changes the state from one of the active states to slee p state if the lin bus goes into sleep mode. for a lin master, software changes state fro m sleep to active where it remains until software sets it back to the sleep state. af ter configuration software does not alter the linstate field during operation. 00 = sleep state (either lmst or lslv is set) 01 = wait for break state (only valid for lslv = 1) 10 = autobaud state (only valid for lslv = 1) 11 = active state (either lmst or lslv is set) txbreaklength ?used in lin mode by the master to control the duration of the transmitted break. 00 = 13 bit times 01 = 14 bit times 10 = 15 bit times 11 = 16 bit times www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 164 lin-uart address compare register the lin-uart address compare register stor es the multi-node network address of the lin-uart. when the mpmd[1] bit of lin-uart control register 0 is set, all incoming address bytes are compared to the value stored in the address compare register. receive interrupts and rda assertions occur only in the event of a match. comp_addr?compare address this 8-bit value is compared to the incoming address bytes. lin-uart baud rate high and low byte registers the lin-uart baud rate high and low byte registers (see table 90 and table 91 ) combine to create a 16-bit baud rate divisor value ( brg[15:0] ) which sets the data transmission rate (baud rate) of the lin-uart. table 89. lin-uart address compare register (uxaddr) bits 7 6 5 4 3 2 1 0 field comp_addr reset 00h r/w r/w addr ff-e205h, ff-e215h table 90. lin-uart baud rate high byte register (uxbrh) bits 7 6 5 4 3 2 1 0 field brh reset 1 r/w r/w addr ff-e206h, ff-e216h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 165 the lin-uart data rate is calculated usin g the following equation for standard uart modes. for lin protocol, the baud rate regist ers must be programmed with the baud period rather than 1/16 baud period. the uart must be disabled wh en updating the baud rate registers because high and low registers must be written independently. the lin-uart data rate is calculated usin g the following equation for standard uart operation: the lin-uart data rate is calculated usin g the following equation for lin mode uart operation: for a given lin-uart data rate, the integer ba ud rate divisor value is calculated using the following equation for standard uart operation: for a given lin-uart data rate, the integer ba ud rate divisor value is calculated using the following equation for lin mode uart operation: table 91. lin-uart baud rate low byte register (uxbrl) bits 7 6 5 4 3 2 1 0 field brl reset 1 r/w r/w addr ff-e207h, ff-e217h note: uart baud rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------- ---------------------- --------------------- ----------------- --------------- = uart data rate (bits/s) system clock frequency (hz) uart baud rate divisor value ------------------- --------------------- --------------------- -------------------- - = uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) ---------------------- --------------------- ----------------- ---------------- ?? ?? = uart baud rate divisor value (brg) round system clock frequency (hz) uart data rate (bits/s) ------------------- --------------------- --------------------- --------------- ?? ?? = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 166 the baud rate error relative to the appropriate baud rate is calculated using the following equation: for reliable communication, the lin-uart baud rate error must never exceed 5 percent. table 92 on page 167 provides information on baud rate errors for popular baud rates and commonly used crystal oscillator frequenc ies for normal uart mode of operation. when the lin-uart is disabled, the baud rate generator functions as a basic 16-bit timer with interrupt on time-out. to configure the baud rate generator as a timer with interrupt on time-out, complete th e following procedure: 1. disable the lin-uart receiver by clearing the ren bit in the lin-uart control 0 register to 0 ( ten bit is asserted, transmit activity may occur). 2. load the appropriate 16-bit count value into the lin-uart baud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the brgctl bit in the lin-uart control 1 regi ster to 1. enable the uart receive interrupt in the interrupt controller. when configured as a general purpose timer, th e brg interrupt interval is calculated using the following equation: uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate ------------------- --------------------- --------------------- ------------------ ----------------- - ?? ?? = uart brg interrupt interval (s) syste m clock period (s) brg[15:0] = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 167 table 92. lin-uart baud rates 20.0 mhz system clock 10.0 mhz system clock desired rate brg divisor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 1 1250.0 0.00 1250.0 n/a n/a n/a 625.0 2 625.0 0.00 625.0 1 625.0 0.00 250.0 5 250.0 0.00 250.0 3208.33-16.67 115.2 11 113.64 -1.19 115.2 5 125.0 8.51 57.6 22 56.82 -1.36 57.6 11 56.8 -1.36 38.4 33 37.88 -1.36 38.4 16 39.1 1.73 19.2 65 19.23 0.16 19.2 33 18.9 0.16 9.60 130 9.62 0.16 9.60 65 9.62 0.16 4.80 260 4.81 0.16 4.80 130 4.81 0.16 2.40 521 2.399 -0.03 2.40 260 2.40 -0.03 1.20 1042 1.199 -0.03 1.20 521 1.20 -0.03 0.60 2083 0.60 0.02 0.60 1042 0.60 -0.03 0.30 4167 0.299 -0.01 0.30 2083 0.30 0.2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 168 5.5296 mhz system clock 3. 579545 mhz system clock desired rate brg divisor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 345.6 38.24 250.0 1223.72-10.51 115.2 3 115.2 0.00 115.2 2111.9-2.90 57.6 657.60.00 57.6 4 55.9 -2.90 38.4 938.40.00 38.4 6 37.3 -2.90 19.2 18 19.2 0.00 19.2 12 18.6 -2.90 9.60 36 9.60 0.00 9.60 23 9.73 1.32 4.80 72 4.80 0.00 4.80 47 4.76 -0.83 2.40 144 2.40 0.00 2.40 93 2.41 0.23 1.20 288 1.20 0.00 1.20 186 1.20 0.23 0.60 576 0.60 0.00 0.60 373 0.60 -0.04 0.30 1152 0.30 0.00 0.30 746 0.30 -0.04 table 92. lin-uart baud rates (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 169 1.8432 mhz system clock desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 n/a n/a n/a 115.2 1 115.2 0.00 57.6 257.60.00 38.4 338.40.00 19.2 619.20.00 9.60 12 9.60 0.00 4.80 24 4.80 0.00 2.40 48 2.40 0.00 1.20 96 1.20 0.00 0.60 192 0.60 0.00 0.30 384 0.30 0.00 table 92. lin-uart baud rates (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y lin-uart zneo ? Z16F series product specification 170 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y infrared encoder/decoder zneo ? Z16F series product specification 171 infrared encoder/decoder the zneo ? Z16F series products contain two fully-functional, high-performance uart to infrared encoder/decoders (endecs). each in frared endec is integrated with an on-chip uart to allow easy communication betw een the zneo and irda physical layer specification, version 1.3-compliant infrar ed transceivers. in frared communication provides secure, reliable, low-cost, point-t o-point communication between pcs, pdas, cell phones, printers, and other infrared-enabled devices. architecture figure 31 displays the architecture of the infrared endec. figure 31. infrared data communication system block diagram operation when the infrared endec is en abled, the transmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infrared transceiver via the txd pin. similarly, data received from th e infrared transceiver is passed to the infrared endec via the rxd pi n, decoded by the infra red endec, and then passed to the uart. communica tion is half-duplex, which means that simultaneous data transmission and reception is not allowed. interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data infrared transceiver rxd txd baud rate clock (endec) zilog ? zhx1810 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y infrared encoder/decoder zneo ? Z16F series product specification 172 the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enable d to use the infrared endec. the infrared endec data rate is calculat ed using the below equation: transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16-clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16-clock period. if the data to be transmitted is 0, a 3-clock high pulse is output following a 7-clock low period. after the 3-clock high pulse, a 6-clock low pulse is output to complete the fu ll 16-clock data period. figure 32 displays irda data transmission. when the infrared endec is enable d, the uart?s txd signal is internal to the zneo Z16F series products while the ir_txd signal is output through the txd pin. figure 32. infrared data transmission infrared data rate (bps) system clock frequency (hz) 16 uart baud rate divisor value ---------------------- --------------------- ----------------- ------------------ ---------------- = baud rate ir_txd uart?s 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3-clock pulse txd clock www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y infrared encoder/decoder zneo ? Z16F series product specification 173 receiving irda data data received from the infrared transceiver via the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate th e demodulated signal (rxd) that drives the uart. each uart/infrared data bit is 16-clocks wide. figure 33 displays data reception. when the infrared endec is enabled, the uar t?s rxd signal is internal to the zneo Z16F series products when the ir_rxd signal is received through the rxd pin. figure 33. infrared data reception the system clock frequency must be at le ast 1.0 mhz to ensure proper reception of the 1.6 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is rese t. when the count reac hes a value of 8, the uart rxd value is updated to reflect the value of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the wi ndow remains open until the count again reaches 8 (or in other words 24 baud clock periods since the previous pulse was detected). this gives the endec a sampling window of minus 4 baudrate clocks to plus 8 baudrate clocks around the expected time of an incoming pulse. if an inco ming pulse is detected inside this window, baud rate uart?s ir_rxd 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8-clock delay clock rxd 16-clock period 16-clock period 16-clock period 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = min. 1.6 s pulse caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y infrared encoder/decoder zneo ? Z16F series product specification 174 this process is repeated. if the incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits for the next falling edge. as each falling edge is detected, the endec clock counter is reset, resynchronizi ng the endec to the incoming signal. this allows the endec to tolerate jitter and baud rate errors in the incoming data stream. resynchronizing the endec does not alter th e operation of the uart, which ultimately receives the data. the uart is only synchron ized to the incoming data stream when a start bit is received. infrared encoder/decoder co ntrol register definitions all infrared endec configuration and status information is set by the uart control registers as defined in the beginning in lin-uart control register definitions on page 152 . to prevent spurious signals during irda data transmission, set the iren bit in the uartx control 1 register to 1 to enable the infra red encoder/decoder befo re enabling the gpio port alternate function fo r the corresponding pin. caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 175 enhanced serial peripheral interface the enhanced serial peripheral interface (espi) supports spi (serial peripheral interface) and inter ic sound (i 2 s) modes of operation. the features of the espi include: ? full-duplex, synchronous, char acter-oriented communication. ? four-wire interface ( ss , sck, mosi, miso). ? transmit and receive buffer regist ers to enable high throughput. ? transfer rates up to maximum of one-fourth the system clock frequency. this is in slave mode. ? error detection. ? dedicated programmable ba ud rate generator (brg). ? data transfer control through polling, interrupt, or dma. architecture the espi is a full-duplex, sync hronous, character-oriented channel that supporting a four-wire interface (serial clock, transmit an d receive data, and slave select). the espi block consists of a shift register, transmit and receive data buffer registers, a baud rate (clock) generator, control/status registers, and a control state machine. transmit and receive transfers are in sync as there is a sing le shift register for both transmit and receive data. figure 34 on page 176 displays a block diagram of the espi. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 176 figure 34. espi block diagram gpio logic and port pins espi state machine baud rate interrupt/ dma logic espi control register espi mode register espi status register espi state register espi brh register espi brl register sck logic peripheral bus ss out ss in miso in miso out mosi in sck in sck out count = 1 ss miso mosi sck 0 shift register 7 transmit data register mosi out generator pin direction control dma requests tx rx interrupt data_out receive data register www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 177 espi signals the four espi signals are: ? master-in/slave-out (miso) ? master-out/slave-in (mosi) ? serial clock (sck) ? slave select ( ss ) the following paragraphs describe these signals in both master and slave modes. the appropriate gpio pins must be conf igured using the gpio alternate function registers. master-in/slave-out the miso pin is configured as an input in a master device and as an output in a slave device. data is transferred to most significant bit first. the miso pin of a slave device is placed in a high-impedance state if the slave is not selected. when th e espi is not enabled, this signal is in a high-imp edance state. the direction of this pin is controlled by the mmen bit of the espi control register. master-out/slave-in the mosi pin is configured as an output in a master device and as an input in a slave device. data is transferred to most significant bit first. when the espi is not enabled, this signal is in a high-impedance state. the di rection of this pin is controlled by the mmen bit of the espi control register. serial clock the sck synchronizes data movement both in and out of the shift register via the mosi and miso pins. in master mode ( mmen = 1 ), the espi?s baud rate generator creates the serial clock and drives it out via its sck pin to the slave devices. in slave mode, the sck pin is an input. slave devices ignore the sck signal unless their ss pin is asserted. the master and slave are each capable of exchanging a charac ter of data during a sequence of numbits clock cycles (see numbits field in the espi mode register on page 195). in both master and slave espi devices, data is shifted on one edge of the sck and is sampled on the opposite edge wh ere data is stable. sck phase and polarity is determined by the phase and clkpol bits in the espi control register on page 193. slave select the ss signal is a bidirectional framing signal with several modes of operation to support spi and other synchronous serial interface protocols. the slave select mode is selected by the ssmd field of the espi mode register. the direction of the ss signal is www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 178 controlled by the ssio bit of the espi mode register. the ss signal is an input on slave devices and is an output on the active master device. slave devices ignore transactions on the bus unless their slave select input is asserted. in spi master mode, additional gpio pins are required to provide slave selects if there is more than one slave device. espi register overview the espi control/status registers are summarized in table 93 . these registers are accessed by either word (16- bit) or byte operations. comparison with basic spi block the espi module includes many enhancements when compared to the simpler spi module in other z8 encore! ? parts. this section highlights the di fferences between the espi module and the spi module as follows: ? transmit and receive data buffer register added to support higher performance. ? multiple interrupt sources (transmit data, re ceive data, errors). spi module only has data transfer complete interrupt. ? dma controller interface (separate transmit and receive interfaces). ? register addresses redefined to fac ilitate 16-bit transfers on the zneo ? Z16F series. ? transmit data command register ? new re gister to facilitate dma interface and improve performance with 16 -bit transfers. ssv and teo f is set on same cycle on which the data register is written. ? control register: ? irqe changed to dirqe. this allows data interrupts to be disabled when using dma but still allow error interrupts. ? str bit on the spi module replac ed with espien1. spien replaced with espien0. this enhancement allows unid irectional transfers which minimizes software or dma overhead. ? birq replaced with brgctl. table 93. espi registers word address even address odd address xxxxx0 data transmit data command xxxxx2 control mode xxxxx4 status state xxxxx6 baud rate high baud rate low www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 179 ? mode register: ? added ssmd field which adds support for loop back and i2s modes. ? moved ssv bit to the transmit data command register as described above. ? added slave select polarity (sspo) to support active high and low slave select on ss pin. ? status register: ? irq split into tdre and rdrf ( separate transmit and receive interrupts). ? replace overrun error with separate transmit under-run and receive overrun. ? state register. ? replaced scken bit with scki. ? replaced tcken with sdi. operation during transfer, data is sent and received simultaneously by both master and slave devices. separate signals are re quired to transmit data, receive data, and the serial clock. when a transfer occurs, a multibit (typically 8-bi t) character is shifted out one data pin and a multi-bit character is simultan eously shifted in on a second data pin. an 8-bit shift register in the master and an 8-bit shift register in the slave is connected as a circular buffer. the espi shift register is buffered to support back-to-back character transfers in high performance applications. a transaction is initiated when th e transmit data register is written in the master device. the value from the data register is transferre d into the shift register and the transaction begins. after the transmit data is loaded into the shift regist er, the transmit data register empty (tdre) status bit asserts, indicating that transmit data register is written with the next value. at the end of each character tran sfer, the shift register value (receive data) is loaded into the receive data re gister. at that point the receive data register full (rdrf) status bit asserts. when software or dma reads the receive data from the receive data register, the rdrf signal deasserts. the master sources the sck and ss signal during the transfer. internal data movement (either by software or dma) to/from the espi block is controlled by the transmit data register empty (tdre) an d receive data register full (rdrf) signals. these signals are read only bits in the espi status register. when either the tdre or rdrf bits assert, an interrupt is sent to the interrupt controller if th e data interrupt request enable (dirqe) bit is set. the tdre and rdrf signals also generate transmit and receive dma requests. in many cases the software application is on ly moving information in one direction. in such a case, either the tdre or rdrf in terrupts/dma requests is disabled to minimize software/dma overhead. unidir ectional data transfer is supported by setting the www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 180 espien1, 0 bits in the control register to 10 or 01 . if the dma engine is being used to move the data, the transmit and receive data interrupts are disabled through the dirqe bit of the control register. in this case error interrupts still occurs and must be handled directly by the software. throughput in master mode the maximum sck rate su pported is one-half the system clock frequency. this is achieved by programming th e value 0001h into the baud rate high/low register pair. though each character is transferre d at this rate, it is unlikely that software interrupt routines or dma keeps up with th is rate. in spi mode the transfer will automatically pause between characters until th e current receive character is read and the next transmit data value is written. in slave mode, the transfer rate is controlle d by the master. as long as the tdre and rdrf interrupt or dma requests are serviced before the next character transfer completes the slave will keep up with the master. in slave mode, the baud rate is restricted to a maximum of one-fourth of the system clock fre quency to allow for synchronization of the sck input to the inte rnal system clock. espi clock phase and polarity control the espi supports four combinations of sck phase and polarity using two bits in the espi control register. the clock polarity bit, clkpol , selects an active high or active low clock and has no effect on the tr ansfer format. the clock phase bit, phase , selects one of two fundamentally different transfer form ats. the data is output a half-cycle before the receive clock edge which provides a half cycle of setup and hold time. table 94 lists the espi clock phase and pola rity operation parameters. transfer format with phase equals zero figure 35 on page 181 displays the timing diagra m for an spi type transfer in which phase = 0 . for spi transfers the clock only toggl es during the character transfer. the two sck waveforms show polarity with clkpol = 0 and with clkpol = 1 . the diagram is table 94. espi clock phase ( phase ) and clock polarity ( clkpol ) operation phase clkpol sck transmit edge sck receive edge sck idle state 0 0 falling rising low 0 1 rising falling high 1 0 rising falling low 1 1 falling rising high www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 181 interpreted as either a master or slave timi ng diagram as the sck miso and mosi pins are directly connected between the master and the slave. figure 35. espi timing when phase = 0 transfer format with phase equals one figure 36 on page 182 displays the timing diagra m for an spi type transfer in which phase = 1 . for spi transfers the clock only togg les during the character transfer. two waveforms are depicted for sck, one for clkpol = 0 , and another for clkpol = 1 . sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 182 figure 36. espi timing when phase = 1 modes of operation this section describes the different modes of data transfer supported by the espi block. the mode is selected by the slave select mode (ssmd) field of the mode register. spi mode this mode is selected by setti ng the ssmd field of the mode register to 000. in this mode, software or dma controls the assertion of the ss signal directly via the ssv bit of the spi transmit data command register. either dma or software is used to control an spi mode transaction. prior to or simultaneousl y with writing the first transmit data byte, software or dma sets the ssv bit. software sets the ssv bit either by performing a byte write to the transmit data comm and register prior to writing the first transmit character to the data register or by performing a word write to the data register address which loads the first transmit character and simultaneously sets the ssv bit. the dma sets the ssv bit via th e command field of the descriptor. the ssv bit is written on the dma command bus prior to or in sync with the first data byte. ss will remain asserted while one or more characters are tr ansferred. there are two mechanisms for deasserting ss at the end of the transaction. one method is used by dma and also by sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 183 software, is to set the teof bit of the transmit data comman d register when the last tdre interrupt or dma request is being serviced (set teof before or simultaneously with writing the last data byte). wh en the last bit of the last character is transmitted, the hardware will automatically d eassert the ssv and teof bits. the second method is for software to directly clear the ssv bit after the transaction completes. if software clears the ssv bit directly, it is not necessary for soft ware to also set the teof bit on the last transmit byte. after writing the last transmit byte, the end of the transaction is detected by waiting for the last rdrf interrupt or monito ring the tfst bit in the espi status register. the transmit underrun and receive overrun errors do not occur in an spi mode master. if the rdrf and tdre requests have not been serviced before the current byte transfer completes, sclk is paused until the data register is read and written. the transmit underrun and receive overrun errors will occur in a slave if the slav e?s software/dma does not keep up with the master data rate. if a transmit underrun occurs in slave mode, the shift register in the slave is loaded with all 1s. in the spi mode, the sck is active only for th e data transfer with one sck period per bit transferred. if the spi bus has multiple slaves, the slave select lines to all or one of the slaves must be controlled independently by software using gpio pins. figure 37 on page 184 displays multiple character transfer in spi mode. note that while character ?n? is being transfe rred using the shift register, so ftware/dma resp onds to the receive request for character n-1 and the transmit request for character n+1. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 184 figure 37. spi mode (ssmd = 000) i2s (inter-ic sound) mode this mode is selected by setting the ssmd field of the mode register to 010. the phase and clkpol bits of the control register must be set to 0. this mode is illustrated in figure 38 on page 185 with ss alternating between consecutiv e frames. a frame consists of a fixed number of data bytes as defined in the dma buffer descriptor or by software. i 2 s (inter-ic sound) mode is ty pically used to transfer left or right channel audio data. the ssv indicates whether the corresponding bytes are left or right channel data. the ssv value must be updated when servicing the tdre interrupt/request for the first byte in a left or write channel frame . this is accomplis hed by performing a word write when writing the first byte of the audio word, whic h updates both the espi data and transmit data command words or by doin g a byte write to update ssv followed by a byte write to the data register. the ss signal leads the data by one sck period. if a dma channel is controlling data transfer, ea ch sequence of left (or right) channel byte is considered a frame with a buffer descrip tor. the ssv bit is de fined in the buffer descriptor command field and is automatically written to the transmit data command bit7 bit6 bit1 bit0 bit7 mosi, miso rx data register bit 6 sck (ssmd = 00, phase = 0, clkpol = 0, sspo = 0) bit0 shift register tdre rdrf rx n-1 tx/rx n-1 tx/rx n tx/rx n+1 empty espi interrupt rx n empty tx n tx n+1 tx n+2 tx data register www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 185 register just prior to or in synchronous with the first data byte of the frame being written. note that the number of bits pe r frame is a value other than an integral number of 8-bits by setting numbits to a value other than 0. example to send 20 bits/frame, set numbits = 5 and read/write 4 bytes per frame. the transmit data must be left justified and the receive data must be right justified. the transaction is terminated wh en the master has no more data to transmit. after the last bit is transferred, sclk stops and ss and ssv returns to their default states. if teof is not set on the last byte, a transmit underrun error occurs at this point. figure 38. i2s mode (ssmd = 010) spi protocol configuration this section describes in detail how to confi gure the espi block for the spi protocol. in the spi protocol the master sources the sck and asserts slave select signals to one or more slaves. the slave select signals are typically active low. spi master operation the espi block is configured for ma ster mode opera tion by setting the mmen bit = 1 in the espictl register. the ssmd field of the espi mode register is set to 000 for spi protocol mode. the phase , clkpol , and wor bits in the espic tl register and the numbits field in the espi mode register must be consistent with the slave spi devices. typically for an spi master ssio = 1 and sspo = 0 . the appropriate gpio pins are bit7 bit0 bit0 bit7 mosi, miso ss bit 7 sck (ssmd = 010, phase = 0, clkpol = 0) frame n frame n + 1 (may be multiple bytes) (sspo = 0) ssv=1 ssv=0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 186 configured for the espi altern ate function on the mosi, mi so, and sck pins. the gpio for the espi ss pin is configured in a lternate function mode as well though software uses any gpio pin(s) to drive one or mo re slave select lines. if the espi ss signal is not used to drive a slave select the ssio bit must still be set to 1 in a single master system. figure 39 and figure 40 displays the espi block conf igured as an spi master. figure 39. espi configured as an spi master in a single master and single slave system figure 40. espi configured as an spi master in a single master and mu ltiple slave system espi master 8-bit shift register bit 0 bit 7 miso mosi sck ss to slave?s ss pin from slave to slave to slave baud rate generator espi master 8-bit shift register bit 0 bit 7 miso mosi sck gpio to slave #2?s ss pin from slaves to slaves to slaves baud rate generator gpio to slave #1?s ss pin www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 187 multi-master spi operation in a multi-master spi system, all sck pins are tied together, all mosi pins are tied together and all miso pins are tied together. all spi pins must be configured in open- drain mode to prevent bus contention. at any time, only one spi device is configured as the master and all other devices on the bus are configured as slaves. the master asserts the ss pin on the selected slave. then, the active master drives the clock and transmit data on the sck and mosi pins to the sck and mosi pins on the slave (inc luding those slaves which are not enabled). the enabled slave dr ives data out its miso pin to the miso master pin. when the espi is configured as a master in a multi-master spi system, the ss pin must be configured as an input. the ss input signal on a device configured as a master must remain high. if the ss signal on the active master goes low (indicating another master is accessing this device as a slave), a collision erro r flag is set in the espi status register. the slave select outputs on a master in a multi- master system must come from gpio pins. spi slave operation the espi block is configured for slave mode operation by setting the mmen bit = 0 in the espictl register and setting the ssio bit = 0 in the espimode register. the ssmd field of the espi mode register is set to 00 for spi protocol mode. the phase , clkpol and wor bits in the espictl register and the numbits field in the espimode register must be set to be consistent with the other spi devices. typically for an spi slave sspo = 0. if the slave has data to send to the master, th e data must be written to the data register before the transaction starts (first edge of sck when ss is asserted). if the data register is not written prior to the slave transac tion, the miso pin outputs all 1s. due to the delay resulting fro m synchronization of the ss and sck input signals to the internal system clock, the maximum sck baud rate which is supported in slave mode is the system clock frequency divided by 8. this rate is controlled by the spi master. figure 41 on page 188 displays the espi configuration in spi slave mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 188 figure 41. espi configured as an spi slave error detection error events detected by the espi block are described in this s ection. error events generate an espi interrupt and se t a bit in the espi status register. the error bits of the espi status register are read/write 1 to clear. transmit underrun a transmit underrun error occurs for a master with ssmd = 10 or 11 when a character transfer completes and tdre = 1. in these modes when a transmit underrun occurs the transfer is aborted (sck will halt and ssv will be deasserted). for a master in spi mode ( ssmd = 00 ) a transmit underrun is not signaled si nce sck will pause and wait for the data register to be written. in slave mode, a transmit underru n error occurs if tdre = 1 at the start of a transfer. when a transmit underrun occurs in slave mo de, espi transmits a character of all 1s. a transmit underrun sets the tund bit in the espi status register to 1. writing 1 to tund clears this error flag. mode fault (multi-master collision) a mode fault indicates when mo re than one master is trying to communicate at the same time (a multi-master collision) in spi mode. th e mode fault is detected when the enabled master?s ss input pin is asserted. for this to happ en the control and mode registers must be configured with mmen = 1, ssio = 0 (ss is an input) and ss input = 0. a mode fault sets the col bit in the espi status register to 1. writing a 1 to col clears this error flag. spi slave 8-bit shift register bit 7 bit 0 miso mosi sck ss from master to master from master from master www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 189 receive overrun a receive overrun error occurs when a transf er completes and the rdrf bit is still set from the previous transfer. a receive overrun sets the rovr bit in the espi status register to 1. writing 1 to rovr clears this error flag . the receive data register is not overwritten and will contain the data from the transfer wh ich initially set the rdrf bit. subsequent received data is lost until the rdrf bit is cleared. slave mode abort in slave mode of operation if the ss pin deasserts before all bits in a character have been transferred, the transaction is aborted. when this condition occurs the abt bit is set in the espi status register. a slave abort e rror resets the slave cont rol logic to the idle state. a slave abort error is also asserted in slave mode, if brgctl = 1 and a brg timeout occurs. when brgctl = 1 is in slave mode, it functions as a wdt monitoring the sck signal. the brg counter is reloaded every time a transition on sck occurs while ss is asserted. the baud rate reload registers must be programmed with a value longer than the expected time between ss assertion and the first sck ed ge, between sck transitions while ss is asserted and between the last sck edge and ss deassertion. a timeout indicates the master is stalled or disabled. writing 1 to abt clears this error flag. espi interrupts espi has a single interrupt output which is asserted when any of the tdre , tund , col , abt , rovr , or rdrf bits are set in the espi status register. the interrupt is a pulse (duration of one system clock) generated when any one of the source bits initially set. the tdre and rdrf interrupts are enabled/disab led through the data interrupt request enable ( dirqe ) bit of the espi control register. a transmit interrupt is asserted by the tdre status bit when the espi block is enabled and the dirqe bit is set. the tdre bit in the status register is cleared automatically when the transmit data register is written or the esp i block is disabled. when the transmit data register value is loaded into the shift register to start a new transfer, the tdre bit will be set again causing a new transmit interrupt. if information is being received but not transmitted the transmit interrupts are elim inated by selecting receive only mode ( espien1,0 = 01 ). a master operates in receive on ly mode however a write to the espi (transmit) data register is still required to initiate the transfer of a character. a receive interrupt is generated by the rdrf status bit when the espi block is enabled; the dirqe bit is set and a character transfer comple tes. at the end of the character transfer, the contents of the shif t register is transferred into the receive data register, causing the rdrf bit to assert. the rdrf bit is cleared when the receive data register is read. if information is being transmitted but not receive d by the software app lication, the receive interrupt is elimin ated by selecting transmit only mode ( espien1,0 = 10 ) in either master or slave modes. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 190 espi error interrupts occur if any of the tund , col , abt , and rovr bits in the espi status register are set. these bits are cleared by writing a 1 to the corresponding bit. if the espi is disabled ( espien1,0 = 00 ), an espi interrupt is generated by a brg timeout. this timer function mu st be enabled by setting the brgctl bit in the espictl register. this timer interrupt does not set an y of the bits of the espi status register. dma interface the assertion of the tdre and rdrf signals generate transmit and receive dma requests (spitxreq, spirxreq), allowing data movement to be handled by a dma controller rather than directly by so ftware. the dma ackn owledges these requests through the spitxack and spirxack signals). inputs allow the ssv and teof bits of the transmit data command register to be co ntrolled by the dma. the spitxreqeof and spirxreqeof outputs to the dma provides an indication that ss has deasserted (transaction complete). if the software application is moving data in only one direction, the espien1,0 bits are set to 10 or 01, allowing a single dma chan nel to control the espi data transfer. for a master, the valid options are transmit only or transmit-receive. for a slave, all options are valid. when a slave is operating in receive only mode, it will transmit characters of all 1s. dma descriptors for espi transmit dma descriptors, the 4-bit cmdstat field of the descriptor is in table 95 format. the ssv bit in the mast er?s transmit buffer descriptor cmdstat field controls the espi ss output. the ssv bit in the descriptor is transferred to the ssv bit in the espi data command register with the first byte of the buffer. if the eof bit is set in the dma descriptor control word, the end of frame signal from the dma (eofsync) will assert coincident with writing the last byte in the buffer to the espi data register, setting the teof bit of the espi data co mmand register. once this last byte has been transferred, the master?s ss output will deassert and the ssv an d teof bits in the data command register will be cleared. the cmdstat field in espi receive dma descriptors has no function. for espi dma descriptors, the 4-bit frame status field of the descriptor has the following format. table 95. espi tx dma descriptor command field reserved reserved reserved ssv table 96. espi tx dma descriptor status field 0 0 col tund www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 191 tund, col, abt, rovr ?see the status register for description of these bits. rss?value of ss associated with last byte written (useful in i2s mode to distinquish left/right channel data). espi baud rate generator in espi master mode, the brg creates a lowe r frequency serial clock (sck) for data transmission synchronization between the master and the external slave. the input to the brg is the system clock. the espi baud rate high and low byte registers combine to form a 16-bit reload value, brg[15:0], for the espi brg. the espi baud rate is calculated using the following equation: minimum baud rate is obtained by setting brg [15:0] to 0000h for a clock divisor value of (2 x 65536 = 131072). when the espi is disabled, the brg functions as a basic 16-bit timer with interrupt on timeout. follow the steps below to configure th e brg as a timer with interrupt on timeout: 1. disable the espi by clearing the espien1 ,0 bits in the espi control register. 2. load the appropriate 16-bit count value into the espi ba ud rate high and low byte registers. 3. enable the brg timer functio n and associated interrupt by setting the brgctl bit in the espi control register to 1. when configured as a general purpose timer, th e spi brg interrupt interval is calculated using the following equation: espi control register definitions espi data register the espi data register (see table 98 ) addresses both the outgoing transmit data register and the incoming receive data register. re ads from the espi data register return the contents of the receive data register. the receive data register is updated with the contents of the shift register at the end of ea ch transfer. writes to the espi data register table 97. espi rx dma descriptor status field 0 rss abt rovr spi baud rate (bps) system clock frequency (hz) 2 brg[15:0] -------------------- --------------------- --------------------- -------------- = spi brg interrupt interval (s) s ystem clock period (s) brg[15:0] = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 192 load the transmit data register unless tdre = 0 . data is shifted out starting with bit 7. the last bit received resi des in bit position 0. with the espi configured as a master, writing a da ta byte to this register initiates the data transmission. with the espi configured as a sl ave, writing a data byte to this register loads the shift register in preparation for the ne xt data transfer with the external master. in either the master or slave modes, if tdre = 0, writes to this register are ignored. when the character length is l ess than 8 bits (as set by the numbits field in the espi mode register), the transmit character must be left justified in the espi data register. a received character of less than 8 bits is right justified (last bit received is in bit position 0). for example, if the espi is configured for 4-bi t characters, the transmit characters must be written to espidata[7:4] and the received characters are read from espidata[3:0]. data?data transmit and/or receive data. wr ites to the espidata register load the shift register. reads from the espidata register return th e value of the receive data register. espi transmit data command register the espi transmit data command register (see table 99 ) provides control of the ss pin when it is configured as an output (m aster mode). the teof and ssv bits are controlled by the dma interface as well as by a bus write to this register. table 98. espi data register (espidata) bits 7 6 5 4 3 2 1 0 field data reset xxxxxxxx r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e260h table 99. espi transmit data command register (espitdcr) bits 7 6 5 4 3 2 1 0 field teof ssv reset 00000000 r/w rrrrrrr/wr/w addr ff_e261h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 193 teof?transmit end of frame this bit is used in master mode to indicate that the data in th e transmit data register is the last byte of the transfer or frame. when the last byte has been sent ss (and ssv) change state and teof automatically clears. 0 = the data in the transmit data register is not the last character in the message. 1 = the data in the transmit data register is the last character in the message. ssv?slave select value when ssio = 1, writes to this regist er controls the value output on the ss pin. see ssmd field of the espi mode register for more details. espi control register the espi control register (see table 100 ) configures the espi for transmit and receive operations. dirqe?data interrupt request enable this bit is used to disable or enable data (tdre and rdrf) interrupts. disabling the data interrupts is needed when controlling data tran sfer by dma or polling. error interrupts are not disabled. to block all espi interrupt sources , clear the espi interru pt enable bit in the interrupt controller. 0 = tdre and rdrf assertions do not cause an interrupt. use this setting if controlling data transf er through dma or by software polling of tdre and rdrf. the tund , col , abt , and rovr bits cause an interrupt. 1 = tdre and rdrf assertions will cause an interrupt. tund, col, abt, and rovr w ill also cause interrupts. use this setting if controlling data tran sfer through interrupt handlers. espien1, espien0?espi enable and direction control 00 = espi block is disabled. brg is used as a gene ral purpose timer by setting brgctl = 1. 01 = receive only mode. use this setting if the soft ware application is receiving data but not sending. tdre will assert, howeve r the transmit interrupt and dma requests will not assert. in slave mode , the transmitted data will be all 1s. table 100. espi control register (espictl) bits 7 6 5 4 3 2 1 0 field dirqe espien1 brgctl phase clkpol wor mmen espien0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e262h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 194 in master mode software must still write to the transmit data register to initiate the transfer. 10 = transmit only mode use this setting in master or slave mode when the software applica tion is sending data but not receiving. rdrf will assert, but receive interrupt and dma requests not occur. 11 = transmit/receive mode use this setting if the software ap plication is both sending and receiving information. both tdre and rdrf will be active. brgctl?baud rate generator control the function of this bit depe nds upon espien1,0. when espien1,0 = 00, this bit allows enabling the brg to provide periodic interrupts. if the espi is disabled ( espien1, espien0 = 00 ): 0 = the brg timer function is disabled. reading the baud rate high an d low registers returns the brg reload value. 1 = the brg timer function and ti me-out interrupt are enabled. reading the baud rate high an d low registers returns the brg counter value. if the espi is enabled: 0 = reading the baud rate high and low registers returns the brg reload value. if mmen = 1 , the brg is enabled to generate sck. if mmen = 0 , the brg is disabled. 1 = reading the baud rate high and low registers returns the brg counter value. if mmen = 1 , the brg is enabled to generate sck. if mmen = 0 , the brg is enabled to provide a slave sck timeout. see slave ab ort error description. if reading the counter one byte at a time while the brg is counting keep in mind that the values will not be in sync. it is recommended to read the counter using word (2-byte) reads. phase?phase select sets the phase relationship of the data to the clock. for more information on operation of the phase bit, see espi clock phase and polarity control on page 180. clkpol?clock polarity 0 = sck idles low (0). 1 = sck idles high (1). wor?wire-or (open-drain) mode enabled 0 = espi signal pins not configured for open-drain. 1 = all four espi signal pins (sck, ss , miso, mosi) configured for open-drain function. this setting is used for multi-master and/or mu lti-slave configurations. caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 195 mmen?espi master mode enable this bit controls the data i/o pin selection and sck direction. 0 = data-out on miso, data-in on mosi (u sed in spi slave mode), sck is an input. 1 = data-out on mosi, data-in on miso (used in spi master mode), sck is an output. espi mode register the espi mode register (see table 101 ) configures the character bit width and mode of the espi io pins. ssmd?slave select mode this field selects the behavior of ss as a framing signal. for a detailed description of these modes, see slave select on page 177. 000 = spi mode when ssio = 1, the ss pin is driven directly from th e ssv bit in the transmit data command register. the master software or dm a must set ssv (or a gpio output if the ss pin is not connected to the appropriate slav e) to the asserted state prior to or on the same clock cycle with which the transmit data register is written with the initial byte. at the end of a frame (after the last rd rf event), ssv is deasserted by software. alternatively, ssv is automatically deass erted by hardware if the teof bit in the transmit data command register is set when the last transmit byte is loaded. in spi mode, sck is active only for data transfer (one clock cycle per bit transferred). 001 = loopback mode when espi is configured as master (mmen = 1) the outputs are deasserted and data is looped from shift register out to shift regi ster in. when espi is configured as a slave (mmen = 0) and ss in asserts, miso (slave output) is tied to mosi (slave input) to provide an a remote loop back (echo) function. 010 = i2s mode in this mode, the value from ssv will be output by the master on the ss pin one sck period before the data and will remain in that state until the start of the next frame. typically this mode is used to send back-to-back frames with ss alternating on each frame. a frame boundary is indicated in the master when ssv changes. a frame boundary table 101. espi mode register (espimode) bits 7 6 5 4 3 2 1 0 field ssmd numbits[2:0] ssio sspo reset 000 000 0 0 r/w r/w r/w r/w r/w addr ff_e263h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 196 is detected in the slave by ss changing state. the ss framing signal will lead the frame by one sck period. in this mode sck will run continuously, starting with the initial ss assertion. frames will run back-t o-back as long as software /dma continue to provide data. the i 2 s protocol (inter ic sound) is used to carry left and right channel audio data with the ss signal indicating which channel is bein g sent. in slave mode, the change in state of ss (low to high or high to low) will trig ger the start of a transaction on the next sck cycle. numbits[2:0]?number of data bi ts per character to transfer this field contains the number of bits to sh ift for each character transfer. for information on valid bit positions when the charac ter length is less than 8-bits, see espi data register description on page 191. 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bits 110 = 6 bits 111 = 7 bits ssio?slave select i/o this bit controls the direction of the ss pin. in single master mode, ssio is set to 1 unless a separate gpio pin is being used to provide the ss output function. in the spi slave or multi-master configuration ssio is set to 0. 0 = ss pin configured as an input (spi slave and multi-master modes) 1 = ss pin configured as an output (spi single master mode) sspo?slave select polarity this bit controls the polarity of the ss pin. 0 = ss is active low. (ssv = 1 corresponds to ss = 0) 1 = ss is active high. (ssv = 1 corresponds to ss = 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 197 espi status register the espi status register (see table 102 ) indicates the current state of the espi. all bits revert to their reset state, if the espi is disabled. tdre?transmit data register empty 0 = transmit data register is full or espi is disabled. 1 = transmit data register is empty. a write to the espi (transmit) data register clears this bit. tund?transmit underrun 0 = a transmit underrun error has not occurred. 1 = a transmit underr un error has occurred. col?collision 0 = a multi-master collision (m ode fault) has not occurred. 1 = a multi-master collision (mod e fault) has been detected. abt?slave mode transaction abort this bit is set if the espi is configured in slave mode, a transaction is occurring and ss deasserts before all bits of a character have been transferred as defined by the numbits field of the espimode register. this bit is al so be set in slave mode by an sck monitor timeout (mmen = 0, brgctl = 1). 0 = a slave mode transaction abort has not occurred. 1 = a slave mode transaction abort has been detected. rovr?receive overrun 0 = a receive overrun error has not occurred. 1 = a receive overrun error has occurred. rdrf?receive data register full 0 = receive data register is empty. 1 = receive data register is full. a read from the espi (receive) data register clears this bit. table 102. espi status register (espistat) bits 7 6 5 4 3 2 1 0 field tdre tund col abt rovr rdrf tfst slas reset 0000 0 001 r/w r r/w*r/w*r/w*r/w* r r r addr ff_e264h r/w* = read access. write a 1 to clear the bit to 0. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 198 tfst?transfer status 0 = no data transfer is currently in progress. 1 = data transfer is currently in progress. slas?slave select reading this bit returns th e current value of the ss exclusive-or?d with the sspo bit. 0 = ss pin is low, if sspo = 0, ss pin is high if sspo = 1 (ss is asserted). 1 = ss pin is high, if sspo = 0, ss pin is low if sspo = 1 (ss is deasserted). espi state register the espi state register (see table 103 ) provides observability of the espi clock, data, and internal state. scki ? serial clock input this bit reflects the state of the serial clock pin. 0 = the sck input pin is low 1 = the sck input pin is high sdi ? serial data input this bit reflects the state of the serial da ta input (mosi or miso depending on the mmen bit). 0 = the serial data input pin is low. 1 = the serial data input pin is high. espistate ? espi state machine indicates the current state of the internal espi state machine. this in formation is intended for manufacturing test. the state values may ch ange in future hardware revisions and are not intended to be used by a software driver. table 104 on page 199 defines the valid states. table 103. espi state register (espistate) bits 7 6 5 4 3 2 1 0 field scki sdi espistate reset 00 0 r/w rr r addr ff_e265h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 199 table 104. espistate values and description espistate value description 00_0000 idle 00_0001 slave wait for sck 00_0010 i2s slave mode start delay 00_0011 i2s slave mode start delay 01_0000 spi master mode start delay 11_0001 i2s master mode start delay 11_0010 i2s master mode start delay 10_1110 bit 7 receive 10_1111 bit 7 transmit 10_1100 bit 6 receive 10_1101 bit 6 transmit 10_1010 bit 5 receive 10_1011 bit 5 transmit 10_1000 bit 4 receive 10_1001 bit 4 transmit 10_0110 bit 3 receive 10_0111 bit 3 transmit 10_0100 bit 2 receive 10_0101 bit 2 transmit 10_0010 bit 1 receive 10_0011 bit 1 transmit 10_0000 bit 0 receive 10_0001 bit 0 transmit www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 200 espi baud rate high a nd low byte registers the espi baud rate high a nd low byte registers (see table 105 and table 106 ) combine to form a 16-bit reload value, brg[15:0], for the espi baud rate generator. the espi baud rate is calculated us ing the following equation: minimum baud rate is obtained by setting brg[15:0] to 0000h for a clock divisor value of (2 x 65536 = 131072) when the espi function is disabled, the brg functions as a basic 16-bit timer with interrupt on time-out. follow the procedure below to configure the brg as a general purpose timer with interrupt on timeout: 1. disable the espi by setting espien[1:0] = 00 in the spi control register. 2. load the appropriate 16-bit count value into the espi ba ud rate high and low byte registers. 3. enable the brg timer function and associated interrupt by setting the brgctl bit in the espi control register to 1. when configured as a general purpose timer, th e spi brg interrupt interval is calculated using the following equation: brh = espi baud rate high byte most significant byte, brg[1 5:8], of the espi baud rate generator?s reload value. table 105. espi baud rate high byte register (espibrh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff_e266h spi baud rate (bps) system clock frequency (hz) 2 brg[15:0] -------------------- --------------------- ---------------------- ------------- = spi brg interrupt interval (s) s ystem clock period (s) brg[15:0] = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 201 brl = espi baud rate low byte least significant byte, brg[7:0], of the espi baud rate genera tor?s reload value. table 106. espi baud rate low byte register (espibrl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/w r/w addr ff_e267h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y enhanced serial peripheral interface zneo ? Z16F series product specification 202 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 203 i 2 c master/slave controller the i 2 c master/slave controller makes the zneo ? Z16F series bus compatible with the i 2 c protocol. the i 2 c bus consists of the serial data signal (sda) and a serial clock (scl) signal bidirectional lines. features of the i 2 c controller include: ? operates in master/slave or slave only modes. ? supports arbitration in a multi-mast er environment (master/slave mode). ? supports data rates up to 400 kbps. ? 7-bit or 10-bit slave address recognition (interrupt only on address match). ? optional general call address recognition. ? optional digital filter on receive sda and scl lines. ? optional interactive receive mo de allows software interp retation of each received address and/or data byte before acknowledging. ? unrestricted number of data bytes per transfer. ? baud rate generator (brg) is used as a ge neral purpose timer with interrupt if the i 2 c controller is disabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 204 architecture figure 42 displays the architecture of the i 2 c controller. figure 42. i 2 c controller block diagram sda scl i2cctl shift i2cdata i2cbrh i2cbrl shift load tx/rx state machine baud rate generator i2cstate register bus i 2 c interrupt i2cistat i2cmode i2cslvad tx and rx dma requests www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 205 i 2 c master/slave cont roller registers table 107 summarizes the i 2 c master/slave controller so ftware-accessible registers. comparison with master mode only i 2 c controller porting code written for the master-only i 2 c controller found on other z8 encore! ? parts to the i 2 c master/slave controller is straight forward. the i2cdata, i2cctl, i2cbrh, and i2cbrl register definitions are not chan ged. the difference between master-only i 2 c controller and i 2 c master/slave controller designs is given below: ? the status register (i2cstate) from the master-only i 2 c controller is split into the interrupt status (i2cistat) re gister and the state (i2cstate) register because there are more interrupt sources. the ack , 10b , tas (now called as) and dss (now called ds) bits formerly in the status regi ster are moved to the state register. ? the i2cstate register is called as i2cdst (diagnostic state) register in the master only mode version. the i2cdst regist er provided diagnostic information. the i2cstate register contains status and state in formation that are useful to software in operational mode. ? the i2cmode register is called as i2cdiag (d iagnostic control) register in the mas- ter only mode version. the i2cmode register provides control for slave modes of operation as well as the most signifi cant two bits of the 10-bit slave address. ? the i2cslvad register is added for programming the slave address. ? the ackv bit in the i2cstate register enables the master to verify the acknowledge from the slave before sending the next byte. table 107. i 2 c master/slave controller registers name abbreviation description i 2 c data i2cdata transmit/receive data register i 2 c interrupt status i2cistat interrupt status register i 2 c control i2cctl control register - basic control functions i 2 c baud rate high i2cbrh high byte of baud rate ge nerator initialization value i 2 c baud rate low i2cbrl low byte of baud rate generator initialization value i 2 c state i2cstate state register i 2 c mode i2cmode selects master or slave modes, 7-bit or 10-bit addressing configure address recognition, defines slave address bits [9:8] i 2 c slave address i2cslvad defines slave address bits [7:0] www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 206 ? support for multi-master environments. if arbitr ation is lost when operating as a master, the arblst bit in the i2cistat register is set and the mode au tomatically switches to slave mode. operation the i 2 c master/slave controller operates in either slave-only mode or master/ slave mode with master arbitration. in master/slave mode, it is used as the only master on the bus or as one of several mast ers on the bus with arbitration. in a multi- master environment, the controller switch es from master to slave mode on losing arbitration. though slave operation is fully supported in master/slave mode, if a device is intended to operate only as a slave, th e slave-only mode is selected. in slave- only mode, the device does not initiate a transaction even if software inadvertently sets the start bit. sda and scl signals i 2 c sends all addresses, data, and acknowledge signals over the sda line, the most- significant bit first. scl is the clock for the i 2 c bus. when the sda and scl pin alternate functions are selected for their respective gpio ports, the pins are automatically configured for open -drain operation. the master is responsible for driving the scl clock signal. during the low period of the clock, a slave holds the scl signal low to su spend the transaction if it is not ready to proceed. the master releases the clock at the end of the low period and notices that the clock remains low instead of returning to a hi gh level. when the slave releases the clock, the i 2 c master continues the transaction. all data is transferred in bytes and there is no limit to the amount of data transferred in on e operation. when transmitting address, data or acknowledge, the sda signal changes in the middle of the low period of scl . when receiving address, data, or ack nowledge, the sda signal is sa mpled in the middle of the high period of scl. a low-pass digital filter is app lied to the sda and sc l receive signals by setting the filter enable ( filten ) bit in the i 2 c control register. when the filter is enabled, any glitch, which is less than a system cl ock period in width is rejected . this filter must be enabled when running in i 2 c fast mode (400 kbps) and is also used at lower data rates. i 2 c interrupts the i 2 c controller contains multiple interrupt sour ces that are combined into one interrupt request signal to the interrupt controller. if the i 2 c controller is enabled, the source of the interrupt is determined by bits, which ar e set in the i2cistat register. if the i 2 c controller is disabled, the brg controller is used to generate general-purpose timer interrupts. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 207 each interrupt source other than the baud rate generator interrupt has an associated bit in the i2cistat register, which clears automatical ly when software reads the register or performs some other task such as r eading or writing the data register. transmit interrupts transmit interrupts ( tdre bit = 1 in i2cistat) occur under the followi ng conditions: ? the transmit data register is empty and the txi bit = 1 in the i 2 c control register. ? the i 2 c controller is enabled, with any one of the following: ? the first bit of a 10-bit address is shifted out. ? the first bit of the final byte of an address is shifted out and the rd bit is deasserted. ? the first bit of a data byte is shifted out. writing to the i 2 c data register always clears the trde bit to 0. receive interrupts receive interrupts ( rdrf bit = 1 in i2cistat) occur when a byte of data has been received by the i 2 c controller. the rdrf bit is cleared by reading from the i 2 c data register. if the rdrf interrupt is not serviced prior to the completion of the next receive byte, the i 2 c controller holds scl low during the last data b it of the next byte until rdrf is cleared to prevent receive overruns. a re ceive interrupt does not occur when a slave receives an address byte or for data bytes fo llowing a slave address that did not match. an exception is if the inte ractive receive mode ( irm ) bit is set in the i2cmode register in which case receive interrupts occur for all r eceive address and data bytes in slave mode. slave address match interrupts slave address match interrupts ( sam bit = 1 in i2cistat) occur when the i 2 c controller is in slave mode and an address is received which matches the unique slave address. the general call address (0000_0000) and startb yte (0000_0001) are recognized if the gce bit = 1 in the i2cmode register. software verifies the rd bit in the i2cistat register to determine if the transaction is a read or write transaction. the general call address and startbyte addresses are also distinguished by the rd bit. the general call address ( gca ) bit of the i2cistat register indicates whether the address match occurred on the unique slave address or the general call/startbyte address. the sam bit clears automatically when the i2ci stat register is read. if configured using the mode[1:0] field of the i 2 c mode register for 7-bit slave addressing, the most significant 7 bits of th e first byte of the transaction are compared against the sla[6:0] bits of the slave address register. if configured for 10-bit slave addressing, the first byte of the transaction is compared against {11110, sla[9:8] ,r/w } and the second byte is compared against sla[7:0] . www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 208 arbitration lost interrupts arbitration lost interrupts ( arblst bit = 1 in i2cistat) occur when the i 2 c controller is in master mode and loses arbitration (outpu ts a 1 on sda and receives a 0 on sda). the i 2 c controller switches to slave mode when th is occurs. this bit clears automatically when the i2cistat register is read. stop/restart interrupts a stop/restart event interrupt ( sprs bit = 1 in i2cistat) occurs when the i 2 c controller is in slave mode and a stop or restart cond ition is received, indi cating the end of the transaction. the rstr bit in the i 2 c state register indicates whether the bit was set due to a stop or restart condition. when a restart o ccurs, a new transaction by the same master is expected to follow. this b it is cleared automatically when the i2cistat register is read. the stop/restart interrupt only occurs on a selected (address match) slave. not acknowledge interrupts not acknowledge interrupts ( ncki bit = 1 in i2cistat) occur in master mode when a not acknowledge is rece ived or sent by the i 2 c controller and the start or stop bit is not set in the i 2 c control register . in master mode the not acknowledge interrupt clears by setting the start or stop bit. when this interrupt occurs in master mode, the i 2 c controller waits until it is cleared before performing any action. in slave mode, the not acknowledge interrupt occurs when a not acknowledge is received in response to the data sent. the ncki bit clears in slave mode when soft ware reads the i2cistat register. general purpose timer interrupt from baud rate generator if the i 2 c controller is disabled ( ien bit in the i2cctl register = 0) and the birq bit in the i2cctl register = 1, an interrupt is ge nerated when the brg counts down to 1. the brg reloads and continues countin g, providing a periodic interrupt. none of the bits in the i2cistat register are set, allowing the brg in the i 2 c controller to be used as a general purpose timer when the i 2 c controller is disabled. start and stop conditions the master generates the start and stop conditions to start or end a transaction. to start a transaction, the i 2 c controller generates a start cond ition by pulling the sda signal low while scl is high. to comp lete a transaction, the i 2 c controller generates a stop condition by creating a low-to-high transition of the sda signal while the scl signal is high. the start and stop events occur when the start and stop bits in the i 2 c control register are written by software to be gin or end a transaction. any byte transfer currently under way finishes, including th e acknowledge phase before the start or stop condition occurs. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 209 software control of i 2 c transactions the i 2 c controller is configured using the i 2 c control and i 2 c mode registers. the mode[1:0] field of the i 2 c mode register allows configuring the i 2 c controller for master/slave or slave only mode and configur es the slave for 7-bit or 10-bit addressing recognition. the baud rate hi gh and low byte registers must be programmed for the i 2 c baud rate in slave mode as well as in mast er mode. in slave mode, the baud rate value programmed must match the master's baud rate within +/- 25% for proper operation. master/slave mode is used for: ? master only operation in a single master, one or more slave i 2 c system. ? master/slave in a multi-master, multi-slave i 2 c system. ? slave only operation in an i 2 c system. in slave-only mode the start bit of the i 2 c control register is ignored (software cannot initiate a master transaction by accident). this restricts the operation to slave only mode and prevents accidental operation in master mode. software controls i 2 c transactions by enabling the i 2 c controller interrupt in the interrupt controller or by polling the i 2 c status register. to use interrupts, the i 2 c interrupt must be enabled in the interrupt controller and followed by executing an ei instruction. the txi bit in the i 2 c control register must be set to enable transmit interrupts. an i 2 c interrupt service routine then verifies the i 2 c status register to determine the cause of the interrupt. to control transactions by polling, the in terrupt bits (tdre, rdrf, sam, arblst, sprs, and ncki) in the i 2 c status register must be polled. the tdre bit asserts regardless of the state of the txi bit. master transactions the following sections describe the master r ead and write transactions to both 7- and 10-bit slaves. master arbitration if a master loses arbitration during the addr ess byte, it releases the sda line, switches to slave mode and monitors the address to determin e if it is selected as a slave. if a master loses arbitration during a tran smit data byte, it releases the sda line and waits for the next stop or start condition. the master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the bus in the same bit time. this loss occurs if more than one master is simultaneously accessing the bus. loss of arbitration occu rs during the address phase (two or more masters accessing different slaves) or duri ng the data phase when the masters are attempting to write differen t data to the same slave. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 210 when a master loses arbitration, software is informed by means of the arbitration lost interrupt. software repeats the sam e transaction again at a later time. a special case occurs when a slave transaction st arts just before software attempts to start a new master transaction by setting the start bit. in this case the state machine enters the slave states before the start bit is set and the i 2 c controller does not arbitrate. if a slave address match occurs and the i 2 c controller receives or transmits data, the start bit is cleared and an arbitration lost interrupt is asserted. software minimizes the chance of this occurring by checking the busy bit in the i2cstate register before initiating a master transaction. if a slave address match does not o ccur, the arbitration lo st interrupt does not occur and the start bit is not cleared. the i 2 c controller initiates the master transaction once the i 2 c bus is no longer busy. master address only transactions it is sometimes appropriate to perform an address-only transaction to determine if a particular slave device is able to respond. th is transaction is perform ed by monitoring the ackv bit in the i2cstate register after th e address has been written to the i2cdata register and the start bit has been set. on ce ackv is set, the ack bit in the i2cstate register determines if the slave is able to co mmunicate. the stop bit must be set in the i2cctl register to terminate the transaction without transfe rring data. for a 10-bit slave address, if the first address byte is acknowle dged, the second address byte must also be sent to determine if the appr opriate slave is responding. another approach is to set both the stop and start bits (for sending a 7-bit address). once both bits are cleared (7-bit address has b een sent and transaction is complete), the ack bit is read to determine if the slave is acknowledged. for a 10-bit slave, set the stop bit after the second tdre interrupt (s econd address byte is being sent). master transaction diagrams in the following transaction diagrams, shaded regions indicate data transferred from the master to the slave and unshaded regions indi cate data transferred from the slave to the master. the transaction field labels are defined as follows: ? s ? start ? w ? write ? a ? acknowledge ? a ? not acknowledge ? p ? stop master write transaction with a 7-bit address figure 43 on page 211 displays the data transfer format from a master to a 7-bit addressed slave. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 211 figure 43. data transfer format - master write transaction with a 7-bit address the procedure for a master transmit operati on to a 7-bit addressed slave is given below: 1. software initializes the mode field in the i 2 c mode register for master/slave mode with either 7-bit or 10-bit slave address. the mode field selects the address width for this node when addressed as a slave, not for the remote slave. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty 4. software responds to the tdre bit by writing a 7-bit slave address plus write bit (=0) to the i 2 c data register. 5. software sets the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. when one bit of address is shifted ou t by the sda signal, the transmit interrupt asserts. 9. software responds by writing the transmit data into the i 2 c data register. 10. the i 2 c controller shifts the rest of the address and write bit out the sda signal. 11. the i 2 c slave sends an acknowledge (by pulling the sda signal low) during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c state register. if the slave does not acknowledge the address byte, the i 2 c controller sets the ncki bit in the i 2 c interrupt status register, sets the ackv bit and clears the ack bit in the i 2 c state register. software responds to th e not acknowledge inte rrupt by setting the stop bit and clearing the txi bit. the i 2 c controller flushes the transmit data register, sends the stop condition on the bus and clears the stop and ncki bits. the transaction is complete (ignore the following steps). 12. the i 2 c controller loads the contents of the i 2 c shift register with the contents of the i 2 c data register. 13. the i 2 c controller shifts the data out of thro ugh the sda signal. when the first bit is sent, the transmit interrupt asserts. 14. if more bytes remain to be sent, return to step 9. s slave address w=0 a data a data a data a/a p/s www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 212 15. when there is no more data to be sent, software respon ds by setting the stop bit of the i 2 c control register (or start b it to initiate a new transaction). 16. if no additional transaction is queued by the master, software clears the txi bit of the i 2 c control register. 17. the i 2 c controller completes tr ansmission of the data on the sda signal. 18. the i 2 c controller sends the stop condition to the i 2 c bus. if the slave terminates the transaction ea rly by responding with a not acknowledge during the transfer, the i 2 c controller asserts the ncki interrupt and halts. software must terminate the transaction by setting either the stop bit (end transaction) or the start bit (end this transaction, start a new one). in this case, it is not necessary for software to set the flush bit of the i2cctl register to flush the data that was previously written but not transmitted. the i 2 c controller hardware automatically flushes transmit data in this not acknowledge case. master write transaction with a 10-bit address figure 44 displays the data transfer format fro m a master to a 10-bit addressed slave. figure 44. data transfer format - master write transaction with 10-bit address the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the read/write control bit (=0). the transmit oper ation is carried out in the same manner as 7-bit addressing. the procedure for a master transmit operation to a 10-bit addressed slave is given below: 1. software initializes the mode field in the i 2 c mode register for master/slave mode with 7- or 10-bit addressing (i 2 c bus protocol allows mixing slave address types). the mode field selects the address width fo r this node when addressed as a slave, not for the remote slave. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts because the i 2 c data register is empty. 4. software responds to the tdre interrupt by writing the first slave address byte (11110xx0). the least-significant bit must be 0 for the write operation. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. s slave address 1st byte w=0 a slave address 2nd byte a data a data a/a f/s note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 213 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. when one bit of address is shifted ou t by the sda signal, the transmit interrupt asserts. 9. software responds by writing the second byte of address in to the contents of the i 2 c data register. 10. the i 2 c controller shifts the rest of the first byte of address and write bit out the sda signal. 11. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c status register. if the slave does not acknowledge the first address byte, the i 2 c controller sets the ncki bit in the i 2 c status register, sets the ackv bit and clears the ack bit in the i 2 c state register. softwa re responds to the not acknow ledge interrupt by setting the stop bit and clearing the txi bit. the i 2 c controller flushes the second address byte from the data register, sends the stop condition on the bus and clears the stop and ncki bits. the transaction is complete (ignore the following steps). 12. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (2nd address byte). 13. the i 2 c controller shifts the second address by te out the sda signal. when the first bit is sent, the transmit interrupt asserts. 14. software responds by writing the da ta to be written out to the i 2 c control register. 15. the i 2 c controller shifts out the rest of the se cond byte of slave address (or ensuing data bytes if looping) by the sda signal. 16. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c status register. if the slave does not acknowledge, see the second paragraph of step 11 above. 17. the i 2 c controller shifts the data out by the s da signal. after the first bit is sent, the transmit interrupt asserts. 18. if more bytes remain to be sent, return to step 14. 19. software responds by asserting the stop bit of the i 2 c control register. 20. the i 2 c controller completes tr ansmission of the data on the sda signal. 21. the i 2 c controller sends the stop condition to the i 2 c bus. if the slave responds with a not acknowledge during the transfer, the i 2 c controller asserts the ncki bit, sets the ackv bit and clears the ack bit in the i 2 c state register and halts. software terminates the transaction by se tting either the stop bit (end transaction) note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 214 or the start bit (end this transaction, st art a new one). the transmit data register is flushed automatically. master read transaction with a 7-bit address figure 45 displays the data transfer format for a read operation to a 7-bit addressed slave. figure 45. data transfer format - master read transaction with 7-bit address the procedure for a master read operatio n to a 7-bit addressed slave is as follows: 1. software initializes the mode field in the i 2 c mode register for master/slave mode with 7- or 10-bit addressing (i 2 c bus protocol allows mixing slave address types). the mode field selects the address width fo r this node when addressed as a slave, not for the remote slave. software asserts the ien bit in the i 2 c control register. 2. software writes the i 2 c data register with a 7-bit slave address plus the read bit (=1). 3. software asserts the start bit of the i 2 c control register. 4. if this is a single byte transfer, software asserts the nak bit of the i 2 c control register so that after the first byte of data has been read by the i 2 c controller, a not acknowledge instructio n is sent to the i 2 c slave. 5. the i 2 c controller sends the start condition. 6. the i 2 c controller sends the address an d read bit out the sda signal. 7. the i 2 c slave acknowledges the address by pulling the sda signal low during the next high period of scl. if the slave does not acknowledge the address byte, the i 2 c controller sets the ncki bit in the i 2 c status register, sets the ackv bit and clears the ack bit in the i 2 c state register. software responds to the not ac knowledge interrupt by setting the stop bit and clearing the txi bit. the i 2 c controller flushes the tran smit data register, sends the stop condition on the bus and clears th e stop and ncki bits. the transaction is complete (ignore th e following steps). 8. the i 2 c controller shifts in the fi rst byte of data from the i 2 c slave on the sda signal. 9. the i 2 c controller asserts the receive interrupt. 10. software responds by reading the i 2 c data register. if the next data byte is to be the last, software must set the nak bit of the i 2 c control register. 11. the i 2 c controller sends a not acknowledge to the i 2 c slave if this is the last byte, else an acknowledge. s slave address r=1 a data a data a p/s www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 215 12. if there are more bytes to transfer, the i 2 c controller returns to step 7. 13. a nak interrupt ( ncki bit in i2cistat) is generated by the i 2 c controller. 14. software responds by setting the stop bit of the i 2 c control register. 15. a stop condition is sent to the i 2 c slave. master read transaction with a 10-bit address figure 46 displays the read transaction fo rmat for a 10-bit addressed slave. figure 46. data transfer format - master read transaction with 10-bit address the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the write control bit. the data transfer procedure for a read oper ation to a 10-bit addressed slave is as follows: 1. software initializes the mode field in the i 2 c mode register for master/slave mode with 7-bit or 10-bit addressing (i 2 c bus protocol allows mixing slave address types). the mode field selects the address width fo r this node when addressed as a slave, not for the remote slave. software asserts the ien bit in the i 2 c control register. 2. software writes 11110b followed by the two most sign ificant address bits and a 0 (write) to the i 2 c data register. 3. software asserts the start bit of the i 2 c control register. 4. the i 2 c controller sends the start condition. 5. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 6. when the first bit is shifted out, a transmit interrupt asserts. 7. software responds by writing the least significant eight bits of address to the i 2 c data register. 8. the i 2 c controller completes shifting of the first address byte. 9. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. if the slave does not acknowledge the address byte, the i 2 c controller sets the ncki bit in the i 2 c status register, sets the ackv bit and clears the ack bit in the i 2 c state register. software responds to the not ac knowledge interrupt by setting the stop bit and clearing the txi bit. the i 2 c controller flushes the tran smit data register, sends s slave address 1st byte w=0 a slave address 2nd byte a s slave address 1st byte r=1 a data adata a p www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 216 the stop condition on the bus and clears the stop and ncki bits. the transaction is complete (ignore th e following steps). 10. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (lower byte of 10 bit address). 11. the i 2 c controller shifts out the next eight bits of address. after the first bit shifts, the i 2 c controller generates a transmit interrupt. 12. software responds by setting the start bit of the i 2 c control register to generate a repeated start. 13. software responds by writing 11110b followed by the 2-bit slave address and a 1 (read) to the i 2 c data register. 14. if you want to read only one by te, software responds by setting the nak bit of the i 2 c control register. 15. after the i 2 c controller shifts out the address bits mentioned in step 9 (second address transfer), the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. if the slave does not acknowledge the address byte, the i 2 c controller sets the ncki bit in the i 2 c status register, sets the ackv bit and clears the ack bit in the i 2 c state register. software responds to the not ac knowledge interrupt by setting the stop bit and clearing the txi bit. the i 2 c controller flushes the tran smit data register, sends the stop condition on the bus and clears th e stop and ncki bits. the transaction is complete (ignore th e following steps). 16. the i 2 c controller sends the repeated start condition. 17. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (third address transfer). 18. the i 2 c controller sends 11110b followed by the two most significant bits of the slave read address and a 1 (read). 19. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. 20. the i 2 c controller shifts in a byte of data from the slave. 21. the i 2 c controller asserts the receive interrupt. 22. software responds by reading the i 2 c data register. if the next data byte is to be the last, software must set the nak bit of the i 2 c control register. 23. the i 2 c controller sends an acknowledg e or not acknowledge to the i 2 c slave based on the nak bit. 24. if there are more bytes to transfer, the i 2 c controller returns to step 18. 25. the i 2 c controller generates a nak interrupt (ncki bit in i2cistat). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 217 26. software responds by setting the stop bit of the i 2 c control register. 27. a stop condition is sent to the i 2 c slave. slave transactions the following sections describe read and write transactions to the i 2 c controller configured for 7-bit and 10-bit slave modes. slave address recognition the following slave address r ecognition options are supported: ? slave 7-bit address recognition mode - if irm = 0 during the address phase and the controller is configured for master/slave or slave 7-bit address mode, the hardware detects a match to the 7-bit slave address defined in the i2cslvad register and generates the slave address match interrupt ( sam bit = 1 in i2cistat register). the i 2 c controller automatically responds during the acknowledge phase with the value in the nak bit of the i2cctl register. ? slave 10-bit address recognition mode - if irm = 0 during the address phase and the controller is configured for master/slave or slave 10-bit address mode, the hardware detects a match to the 10-bit slave address defined in the i2cmode and i2cslvad registers and generates the sl ave address match interrupt ( sam bit = 1 in i2cistat register). the i 2 c controller automatically responds during the acknowledge phase with the value in the nak bit of the i2cctl register. ? general call and startbyte address recognition - if gce = 1 and irm = 0 during the address phase and the controller is configured fo r master/slave or slave in either 7- or 10-bit address mode, the hardware detect s a match to the general call address or start byte and generates the slave address match interrupt. a general call address is a 7-bit address of all 0?s with the r/ w bit = 0. a start byte is a 7-bit address of all 0?s with the r/ w bit = 1. the sam and gca bits are set in the i2cistat register. the rd bit in the i2cistat register distin guishes a general call address from a start byte (= 0 for general call address). for a general call address, the i 2 c controller automatically responds during the address acknowledge phase with the value in the nak bit of the i2cctl register. if software processes the data bytes associated with the gca bit, the irm bit is optionally set following the sam interrupt to allow software to examine each received data byte be fore deciding to set or clear the nak bit. a start byte will not be acknowle dged (requirement the i 2 c specification). ? software address recognition - to disabl e the hardware address recognition, the irm bit must be set = 1 prior to the reception of the address byte(s). when irm = 1 each received byte generates a receive interrupt ( rdrf = 1 in the i2cistat register). software must examine each byte and determine whether to set or clear the nak bit. the slave holds scl low during the ackno wledge phase until software responds by writing to the i2cctl register. the value written to the nak bit is used by the controller to drive the i 2 c bus, then releasing the scl. the sam and gca bits are not www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 218 set when irm = 1 during the address phase, but the rd bit is updated ba sed on the first address byte. slave transaction diagrams in the following transaction diagrams, shaded regions indicate data transferred from the master to the slave and unshaded regions indi cate data transferred from the slave to the master. the transaction field labels are defined as follows: ? s ? start ? w ? write ? a ? acknowledge ? a ? not acknowledge ? p ? stop slave receive transaction with 7-bit address the data transfer format for writing data fro m master to slave in 7-bit address mode is shown in figure 47 . the following procedure describes the i 2 c master/slave controller operating as a slave in 7-bit addressing mode, receiving data from the bus master. figure 47. data transfer format - slave receive transaction with 7-bit address 1. software configures the contro ller for operation as a slave in 7-bit addressing mode as follows. ? initialize the mode field in the i 2 c mode register for either slave-only mode or master/slave mode with 7-bit addressing. ? optionally set the gce bit ? initialize the sla [6:0] bits in the i 2 c slave address register. ? set ien = 1 in the i 2 c control register. set nak = 0 in the i 2 c control register. ? program the baud rate high and low byte registers for the i 2 c baud rate. 2. the bus master initiates a transfer, send ing the address byte. the slave mode i 2 c controller recognizes its ow n address and detects the r/ w bit = 0 (write from master to slave). the i 2 c controller acknowledges, indicatin g it is available to accept the transaction.the sam bit in the i2cistat register is set = 1, causing an interrupt. the rd bit in the i2cistat register is set = 0, indicating a write to the slave. the i 2 c controller holds the scl signal low, waiting for software to load the first data byte. s slave address w=0 a data a data a data a/a p/s www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 219 3. software responds to the in terrupt by reading the i2cistat register (which clears the sam bit). after verifying that the sam bit = 1, software checks the rd bit. when rd = 0, no immediate action is required until the firs t byte of data is received. if software is only able to accept a single byte it sets the nak bit in the i2cctl register at this time. 4. the master detects the acknowledge and sends the byte of data. 5. the i 2 c controller receives the data byte and responds with acknowledge or not acknowledge depending on the state of the nak bit in the i2cctl register. the i 2 c controller generates the receive data interrupt by setting the rdrf bit in the i2cistat register. 6. software responds by reading th e i2cistat register, finding the rdrf bit=1 and reading the i2cdata register clearing the rdrf bit. if software accepts only one more data byte, it sets the nak bit in the i2cctl register. 7. the master and slave loop on steps 4?6 until the master detect s a not acknowledge instruction or runs out of data to send. 8. the master sends the stop or restart sign al on the bus. either of these signals cause the i 2 c controller to assert the stop interrupt (stop bit = 1 in the i2cistat register). when the slave receive data fro m the master, software takes no action in response to the stop interrupt other than reading the i2cistat register, clearing the stop bit in the i2cistat register. slave receive transaction with 10-bit address the data transfer format for writing data fro m master to slave with 10-bit addressing is shown in figure 48 . the following procedure describes the i 2 c master/slave controller operating as a slave in 10-bit addressing mode, receiving data from the bus master. s figure 48. data transfer format - slave receive transaction with 10-bit address 1. software configures the controller for operation as a slave in 10-bit addressing mode as follows. ? initialize the mode field in the i2cm ode register for either slave-only mode or master/slave mode with 10-bit addressing. ? optionally set the gce bit. ? initialize the sla [7:0] bits in the i2cslvad register and the sla [9:8] bits in the i2cmode register. ? set ien = 1 in the i2cctl register. set nak = 0 in the i 2 c control register. ? program the baud rate high and low byte registers for the i 2 c baud rate. s slave address 1st byte w=0 a slave address 2nd byte a data a data a/a p/s www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 220 2. the master initiates a tr ansfer by sending the fi rst address byte. the i 2 c controller recognizes the start of a 10-bit address with a match to sla [9:8] and detects the r/ w bit = 0 (write from master to slave). the i 2 c controller acknowledg es, indicating that it is available to accept the transaction. 3. the master sends the second address byte. the slave mode i 2 c controller detects an address match between the second address byte and sla [7:0]. the sam bit in the i2cistat register is set = 1, causing an interrupt. the rd bit is set = 0, indicating a write to the slave. the i 2 c controller acknowledges, in dicating it is available to accept the data. 4. software responds to the in terrupt by reading the i2cistat register, which clears the sam bit. when rd = 0, no immediate action is taken by software until the first byte of data is received. if software is only able to accept a single byte it sets the nak bit in the i2cctl register. 5. the master detects the acknowledge and sends the first byte of data. 6. the i 2 c controller receives the first byte and responds with acknowledge or not acknowledge, depending on the state of the nak bit in the i2cctl register. the i 2 c controller generates the receive data interrupt by setting the rdrf bit in the i2cistat register. 7. software responds by reading th e i2cistat register, finding the rdrf bit = 1 and then reading the i2cdata register, which clears the rdrf bit. if software accepts only one more data byte, it sets the nak bit in the i2cctl register. 8. the master and slave loops on steps 5?7 until the master detects a no t acknowledge instruction or runs out of data to send. 9. the master sends the stop or restart sign al on the bus. either of these signals cause the i 2 c controller to assert the stop interrupt (stop bit = 1 in the i2cistat register). when the slave receive data fro m the master, software takes no action in response to the stop interrupt other than reading the i2cistat register, clearing the stop bit. slave transmit transaction with 7-bit address the data transfer format for a master readin g data from a slave in 7-bit address mode is shown in figure 49 . the following procedure describes the i 2 c master/slave controller operating as a slave in 7-bit addressing mode, transmitting data to the bus master. figure 49. data transfer format - slave transmit transaction with 7-bit address s slave address r=1 a data a data a p/s www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 221 1. software configures the contro ller for operation as a slave in 7-bit addressing mode as follows. ? initialize the mode field in the i 2 c mode register for either slave-only mode or master/slave mode with 7-bit addressing. ? optionally set the gce bit. ? initialize the sla [6:0] bits in the i 2 c slave address register. ? set ien = 1 in the i 2 c control register. set nak = 0 in the i 2 c control register. ? program the baud rate high and low byte registers for the i 2 c baud rate. 2. the master initiates a tr ansfer, sending the address byte. the slave mode i 2 c controller finds an address match and detects the r/ w bit = 1 (read by master from slave). the i 2 c controller acknowledges, indicating that it is ready to accept the transaction.the sam bit in the i2cistat register is set = 1, causing an interrupt. the rd bit is set = 1, indicati ng a read from the slave. 3. software responds to the interrupt by reading the i2cistat register, clearing the sam bit. when rd = 1, software responds by loading the first data byte into the i2cdata register. software sets the txi bit in the i2cctl register to enable transmit interrupts. when the master initiates the data transfer, the i 2 c controller holds scl low until software has written the first data byte to the i2cdata register. 4. scl is released and the first data byte is shifted out. 5. when the first bit of the first data byte is transferred, the i 2 c controller sets the tdre bit, which asserts the transmit data interrupt. 6. software responds to the transmit data interrupt ( tdre = 1) by loading the next data byte into the i2cdata register, which clears tdre . 7. when the master receives the data by te, the master transm its an acknowledge instruction (or not acknowledge inst ruction for the last data byte). 8. the bus cycles through steps 5?7 until the last byte has been transferred. if software has not yet loaded the next da ta byte when the master brin gs scl low to transfer the most significant data bit, the slave i 2 c controller holds scl low until the data register is written. when the slave receives a not acknowledge instruction, the i 2 c controller sets the ncki bit in the i2cistat register and ge nerates the not ackno wledge interrupt. 9. software responds to the not ac knowledge interrupt by clearing the txi bit in the i2cctl register and by asserting the flush bit of the i2cctl register to empty the data register. 10. when the master completes the last ackno wledge cycle, it asserts the stop or restart condition on the bus. 11. the slave i 2 c controller asserts the stop/restart interrupt (set sprs bit in i2cistat register). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 222 12. software responds to the stop/restart in terrupt by reading the i2cistat register which clears the sprs bit. slave transmit (master read) transaction with 10-bit address figure 50 displays the data transfer format for a master reading data from a slave with 10- bit addressing. figure 50. data transfer format - slave transmit transaction with 10-bit address the following procedure describes the i 2 c master/slave controller operating as a slave in 10-bit addressing mode, transm itting data to the bus master: 1. software configures the controller for operation as a slave in 10-bit addressing mode. ? initialize the mode field in the i 2 c mode register for either slave-only mode or master/slave mode with 10-bit addressing. ? optionally set the gce bit. ? initialize the sla [7:0] bits in the i2cslvad register and sla [9:8] in the i2cmode register. ? set ien = 1, nak = 0 in the i 2 c control register. ? program the baud rate high and low byte registers for the i 2 c baud rate. 2. the master initiates a transfer , sending the first address byte. the slave mode i 2 c controller recognizes the start of a 10-bit address with a match to sla [9:8] and detects the r/ w bit = 0 (write from master to slave). the i 2 c controller acknowledges, indicating that it is available to accept the transaction. 3. the master sends the second address byte. the slave mode i 2 c controller compares the second address byte with the value in sla [7:0]. if there is a match, the sam bit in the i2cistat register is set = 1, causi ng a slave address match interrupt. the rd bit is set = 0, indicating a write to the slave. if a match occurs, the i 2 c controller acknowledges on the i 2 c bus, indicating that it is available to accept the data. 4. software responds to the slave address match interrupt by reading the i2cistat register which clears the sam bit. when the rd bit = 0, no further action is required. 5. the master notifies the acknowledge and se nds a restart instruction, followed by the first address byte with the r/ w = 1. the slave mode i 2 c controller re cognizes the restart followed by the first ad dress byte with a match to sla [9:8] and detects the r/ w = 1 (master reads from slave). the slave i 2 c controller sets the sam bit in the s slave address 1st byte w=0 a slave address 2nd byte a s slave address 1st byte r=1 a data adata a p www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 223 i2cistat register, which causes the slave address match interrupt. the rd bit is set = 1. the slave mode i 2 c controller acknowl edges on the bus. 6. software responds to the interrupt by reading the i2cistat register, clearing the sam bit. software loads the initial data byte into the i2cdata register and sets the txi bit in the i2cctl register. 7. the master starts the data transfer by asserting scl low. once the i 2 c controller has data available to transmit the scl is relea sed and the master proceeds to shift the first data byte. 8. when the first bit of the first data byte is transferred, the i 2 c controller sets the tdre bit, which asserts the transmit data interrupt. 9. software responds to the tran smit data interrupt by loading the next data byte into the i2cdata register. 10. the i 2 c master shifts in the remainder of th e data byte. the ma ster transmits the acknowledge (or not acknowledge for the last data byte). 11. the bus cycles through steps 7?10 until the last byte has be en transferred. if software has not yet loaded the next da ta byte when the master brin gs scl low to transfer the most significant data bit, the slave i 2 c controller holds scl low until the data register is written. when the slave receives a not acknowledge, the i 2 c controller sets the ncki bit in the i2cistat register and generates the nak interrupt. 12. software responds to the na k interrupt by clearing the txi bit in the i2cctl register and by asserting the flush bit of the i2cctl register. 13. when the master has completed the acknowle dge cycle of the last transfer it asserts the stop or restart condition on the bus. 14. the slave i 2 c controller asserts the stop/restart interrupt (set sprs bit in i2cistat register). 15. software responds to the stop interrupt by reading the i2cistat register, clearing the sprs bit. dma control of i 2 c transactions the dma engine is configured to suppor t transmit and receive dma requests from the i 2 c controller. the i 2 c data interrupt requests must be disabled by setting the dmaif bit in the i 2 c mode register and clearing the txi bit in the i 2 c control register. this allows error condition interrupts to be handled by software while da ta movement is handled by the dma engine. the dma interface on the i 2 c controller is intended to su pport data transfer but not master mode address byte transfer. the star t, stop, and nak bits must be controlled by software. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 224 a summary of i 2 c transfer of data using the dma follows. master write transaction with data dma ? configure the selected dma channel for i 2 c transmit. the ieob bit must be set in the dmactl register for the last buffer to be transferred. ? the i 2 c interrupt must be enabled in the interrupt controller to alert software of any i 2 c error conditions. a not acknow ledge interrupt occurs on the last byte transferred. ? the i 2 c master/slave must be configured as defined in the sections above describing master mode transactions. the txi bit in the i2cctl register must be cleared. ? initiate the i 2 c transaction as described in the master address only transactions section, using the ackv and ack bits in the i2cstate regi ster to determine if the slave acknowledges. ? set the dmaif bit in the i2cmode register. ? the dma transfers the data, which is to be transmitte d to the slave. ? when the dma interrupt occurs, poll the i2 cstat register until the tdre bit = 1. this ensures that the i 2 c master/slave hardware has commenced transmitting the last byte written by the dma. ? set the stop bit in the i2cctl register. the stop bit is polled by software to determine when the transactio n is actually completed. ? clear the dmaif bit in the i2cmode register. the following procedure describes the i 2 c master/slave controller operating as a slave in 10-bit addressing mode, transm itting data to the bus master. if the slave sends a not acknowledge prior to the last byte, a not acknowledge interrupt occurs. software must respond to this interr upt by clearing the dm aif bit and setting the stop bit to end the transaction. master read transaction with data dma in master read transactions, the master is responsible for the acknowledge for each data byte transferred. the master software must set the nak bit after the next to the last data byte has been received or while the last byte is being received. the dma supports this by setting the dma watermark to 0x01, which resu lts in a dma interrupt when the next to the last byte has been receiv ed. a dma interrupt also occu rs when the last byte is received. otherwise, the sequence is similar to that described above for the master write transaction. ? configure the selected dma channel for i 2 c receive. the ieob bit must be set in the dmactl register for the last buffer to be tr ansferred. typically one buffer is defined with a transfer length of n where n bytes ar e expected to be read from the slave. the watermark is set to 1 by writin g a 0x01 to dmaxlar[23:16]. note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 225 ? the i 2 c interrupt must be enabled in the interrupt controller to alert software of any i 2 c error conditions. a not acknow ledge interrupt occurs on the last byte transferred. ? the i 2 c master/slave must be configured as de fined in the sections above describing master mode transactions. the txi bit in the i2cctl register must be cleared. ? initiate the i 2 c transaction as described in the master address only transactions section, using the ackv and ack bits in the i2cstate regi ster to determine if the slave acknowledges. do not set the stop bit unless ackv =1 and ack =0 (slave did not acknowledge). ? set the dmaif bit in the i2cmode register. ? the dma transfers the data to memory as it is receiv ed from the slave. ? when the first dma interrupt oc curs indicating the (n-1)st byte has been received, the nak bit must be set in the i2cctl register. ? when the second dma interrupt occurs, it indicates that the nth byte has been received. set the stop bit in the i2cctl regi ster. the stop bit is polled by software to determine when the transac tion is actually completed. ? clear the dmaif bit in the i2cmode register. slave write transaction with data dma in a transaction where the i 2 c master/slave operates as a slav e, receiving data written by a master, the software must set the nak bit after the n-1st byte h as been received or during the reception of the last byte. as in the ma ster read transaction described above, the watermark dma interrupt is used to notify software when the n-1st byte has been received. ? configure the selected dma channel for i 2 c receive. the ieob bit must be set in the dmactl register for the last buffer to be transferred. typically one buffer will be defined with a transfer length of n where n bytes are expected to be received from the master. the watermark is set to 1 by writing a 0x01 to dmaxlar[23:16]. ? the i 2 c interrupt must be enabled in the interrupt controller to alert software of any i 2 c error conditions. ? the i 2 c master/slave must be configured as defined in the sections above describing slave mode transactions. the txi bit in the i2cctl register must be cleared. ? when the sam interrupt occurs, set the dmaif bit in the i2cmode register. ? the dma transfers the data to memory as it is received from the master. ? when the first dma interrupt occurs indicati ng that the (n-1)st by te is received, the nak bit must be set in the i2cctl register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 226 ? when the second dma interrupt occurs, it in dicates that the nth byte is received. a stop i 2 c interrupt occurs ( sprs bit set in the i2cstat register) when the master issues the stop (or restart) condition. ? clear the dmaif bit in the i2cmode register. slave read transaction with data dma in this transaction the i 2 c master/slave operates as a slav e, sending data to the master. ? configure the selected dma channel for i 2 c transmit. the ieob bit must be set in the dmactl register for the last buffer to be transferred. typically a single buffer with a transfer length of n is defined. ? the i 2 c interrupt must be enabled in the interrupt controller to alert software of any i 2 c error conditions. a not acknowle dge interrupt occurs on th e last byte transferred. ? the i 2 c master/slave must be configured as defined in the sections above describing slave mode transactions. the txi bit in the i2cctl register must be cleared. ? when the sam interrupt occurs, set the dmaif bit in the i2cmode register. ? the dma transfers the data to be transmitted to the master. ? when the dma interrupt occurs, the last byte is being transferred to the master. the master must send a not acknowledge for this last byte, setting the ncki bit in the i2cstat register and generating the i 2 c interrupt. a stop or restart interrupt ( sprs bit set in i2cstat register) follows. ? clear the dmaif bit in the i2cmode register. if the master sends a not acknowledge prior to the last byte, software responds to the not acknowledge interrupt by clearing the dmaif bit. note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 227 i 2 c control register definitions the following section describes the i 2 c control registers. i 2 c data register the i 2 c data register (see table 108 ) holds the data that is to be loaded into the shift register to transmit onto the i 2 c bus. this register also hold s data that is loaded from the shift register after it is received from the i 2 c bus. the i 2 c shift register is not accessible in the register file address space, but is used only to buffer incoming and outgoing data. writes by software to the i2cdata register are blocked if a slave write transaction is underway (i 2 c controller in slave mode, data being received). i 2 c interrupt status register the read-only i 2 c interrupt status register (see table 109 ) indicates the cause of any current i 2 c interrupt and provides status of the i 2 c controller . when an interrupt occurs , one or more of the tdre , rdrf , sam , arblst , sprs or ncki bits is set . the gca and rd bits do not generate an interrupt but ra ther provide status associated with the sam bit interrupt. tdre?transmit data register empty when the i 2 c controller is enabled, this bit is 1 if the i 2 c data register is empty. when set, the i 2 c controller generates an in terrupt, except when the i 2 c controller is shifting in table 108. i 2 c data register (i2cdata) bits 7 6 5 4 3 2 1 0 field data reset 0 r/w r/w addr ff-e240h table 109. i 2 c interrupt status register (i2cistat) bits 7 6 5 4 3 2 1 0 field tdre rdrf sam gca rd arblst sprs ncki reset 10000000 r/w rrrrrrrr addr ff-e241h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 228 data during the reception of a byte or when shifting an address and the rd bit is set. this bit clears by writing to the i2cdata register. rdrf?receive data register full this bit is set = 1 when the i 2 c controller is enabled and the i 2 c controller has received a byte of data. when asserted, this bit causes the i 2 c controller to gene rate an interrupt. this bit clears by reading the i2cdata register. sam?slave address match this bit is set = 1 if the i 2 c controller is enabled in slave mode and an address is received which matches the unique sl ave address or general call address (if enabled by the gce bit in the i 2 c mode register). in 10-bit addressing mo de, this bit is not set until a match is achieved on both address bytes. when this bit is set, the rd and gca bits are also valid. this bit clears by reading the i2cistat register. gca?general call address this bit is set in slave mode when the gene ral call address or start byte is recognized (in either 7- or 10-bit slave mode). the gce bit in the i 2 c mode register must be set to enable recognition of the general call address and start byte. this bit clears when ien = 0 and is updated following the first addr ess byte of each slave mode transaction. a general call address is dist inguished from a start byte by the value of the rd bit (rd = 0 for general call address, 1 for start byte). rd?read this bit indicates the direction of transfer of the data. it is set when the master is reading data from the slave. this bit ma tches the least-significant bit of the address byte after the start condition occurs (for both master and slave modes). this bit clears when ien = 0 and is updated following the first address byte of each transaction. arblst?arbitration lost this bit is set when the i 2 c controller is enabled in mast er mode and loses arbitration (outputs a 1 on sda and receives a 0 on sda). the arblst bit clears when the i2cistat register is read. sprs?stop/restart condition interrupt this bit is set when the i 2 c controller is enabled in slav e mode and detects a stop or restart condition during a transaction directed to this slave. this bit clears when the i2cistat register is read. read the rstr bit of the i2cstate register to determine whether the interrupt was caused by a stop or restart condition. ncki?nak interrupt in master mode, this bit is set when a not acknow ledge condition is received or sent and neither the start nor the stop bit is active. in master mode, this bit is cleared only by setting the start or stop bits. in slave mode, this bit is set when a no t acknowledge condition is received (master reading data from slave), indica ting the master is finished reading. a stop or restart condition follows. in slave mode this bit clears when the i2 cistat register is read. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 229 i 2 c control register the i 2 c control register (see table 110 ) enables and configures the i 2 c operation. r/w1 - bit is set (write 1) but not cleared. ien?i 2 c enable this bit enables the i 2 c controller. start?send start condition when set, this bit causes the i 2 c controller (when configured as the master) to send the start condition. once asserted , it is cleared by the i 2 c controller after it sends the start condition or by deasserting the ien bit. if this bit is 1, it ca nnot be cleared by writing to the bit. after this bit is set, the start condit ion is sent if there is data in the i2cdata or i2cshift register. if there is no data in one of these registers, the i 2 c controller waits until data is loaded. if this bit is set while the i 2 c controller is shifting out data, it generates a restart condition after the by te shifts and the acknowledge phase completes. if the stop bit is also set, it al so waits until the stop condition is sent before the start condition. if start is set while a slave mode transaction is underway to this device, the start bit is cleared and arblst bit in the interrupt status register will be set. stop?send stop condition when set, this bit causes the i 2 c controller (when configured as the master) to send the stop condition after the byte in the i 2 c shift register has comple ted transmission or after a byte has been received in a receive operatio n. when set, this bit is reset by the i 2 c controller after a stop condition has been sent or by deasserting the ien bit. if this bit is 1, it cannot be cleared to 0 by writing to the register. if stop is set while a slave mode transaction is underway, the stop bit will be cleared by hardware. birq?baud rate generator interrupt request this bit is igno red when the i 2 c controller is enabled. if this bit is set = 1 when the i 2 c controller is disabled ( ien = 0) the baud rate generator is used as an additional timer causing an interrupt to occur every time the baud rate generator counts down to one. the baud rate generator runs continuously in this mode, generatin g periodic interrupts. table 110. i 2 c control register (i2cctl) bits 7 6 5 4 3 2 1 0 field ien start stop birq txi nak flush filten reset 00000000 r/w r/w r/w1 r/w1 r/w r/w r/w1 r/w r/w addr ff-e242h note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 230 txi?enable tdre interrupts this bit enables interrupts when the i 2 c data register is empty. nak?send nak setting this bit sends a not ac knowledge condition after the ne xt byte of data has been received. it is automatically deasserted af ter the not acknowledge is sent or the ien bit is cleared. if this bit is 1, it cannot be cleared to 0 by writing to the register. flush?flush data setting this bit clears the i 2 c data register and sets the tdre bit to 1. th is bit allows flushing of the i 2 c data register when an nak conditi on is received after the next data byte has been written to the i 2 c data register. reading this bit always returns 0. filten?i 2 c signal filter enable setting this bit enables low-pass digital filters on the sda and scl input signals. this function provides the spike supp ression filter required in i2c fast mode. these filters reject any input pulse with periods less than a full system clock cycle. the filters introduce a 3-system clock cycle latency on the inputs. i 2 c baud rate high and low byte registers the i 2 c baud rate high and low byte registers (see table 111 and table 112 on page 231) combine to form a 16-bit reload value, brg [15:0], for the i 2 c baud rate generator. the baud rate high and low byte re gisters must be programmed for the i 2 c baud rate in slave mode as well as in master mode. in sl ave mode, the baud rate value programmed must match the master's baud rate within +/- 25% for proper operation. the i 2 c baud rate is calculated using the below equation. if brg = 0000h , use 10000h in the equation. : . table 111. i 2 c baud rate high byte register (i2cbrh) bits 7 6 5 4 3 2 1 0 field brh reset ffh r/w r/w addr ff-e243h note: i 2 c baud rate (bps) system clock frequency (hz) 4 brg[15:0] --------------------- --------------------- ------------------ ---------------- = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 231 brh = i 2 c baud rate high byte most significant byte, brg [15:8], of the i 2 c baud rate genera tor?s reload value. if the diag bit in the i 2 c mode register is set to 1, a read of the i2cbrh register returns the current value of the i 2 c baud rate counter[15:8]. brl = i 2 c baud rate low byte least significant byte, brg[7:0], of the i 2 c baud rate generator?s reload value. if the diag bit in the i 2 c mode register is set to 1, a re ad of the i2cbrl register returns the current value of the i 2 c baud rate counter[7:0]. i 2 c state register the read only i 2 c state register provides information on the state of the i 2 c bus and the i 2 c bus controller. when the diag bit of the i 2 c mode register is cleared, this register provides information on the internal state of the i 2 c controller and i 2 c bus as shown in table 113 . when the diag bit of the i 2 c mode register is set, this re gister returns the value of the i 2 c controller state machine as shown in table 114 on page 232. ackv?ack valid this bit is set if sending da ta (master or slave) and the ack bit in this register is valid for the byte just transmitted. this b it is monitored if it is appropriate for software to verify the ack value before writing the next byte to be sent . to operate in this mode, the data register table 112. i 2 c baud rate low byte register (i2cbrl) bits 7 6 5 4 3 2 1 0 field brl reset ffh r/w r/w addr ff-e244h table 113. i 2 c state register (i2cstate) - description when diag = 0 bits 7 6 5 4 3 2 1 0 field ackv ack as ds 10b rstr sclout busy reset 000000xx r/w rrrrrrrr addr ff-e245h note: note: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 232 must not be written when tdre asserts; instead, software waits for ackv to assert. this bit clears when transmission of the next byte be gins or the transaction is ended by a stop or restart condition. ack?acknowledge this bit indicates the status of the acknowledge for the last byte transmitted or received. this bit is set for an acknowledge a nd cleared for a not acknowledge condition. as?address state this bit is active high wh ile the address is being transferred on the i 2 c bus. ds?data state this bit is active high while the data is being transferred on the i 2 c bus. 10b?this bit indicates whether a 10 or 7-b it address is being transmitted when operating as a master. after the start bit is set, if the five most-significant bits of the address are 11110b , this bit is set. when set, it is reset once the address has been sent. rstr?restart this bit is updated each time a stop or restart interrupt occurs ( sprs bit set in i2cistat register). 0 = stop condition 1 = restart condition sclout?serial clock output current value of serial clock being output on to the bus. the actual values of the scl and sda signals on the i 2 c bus is observed via the gpio input register. busy?i 2 c bus busy 0 = no activity on the i 2 c bus. 1 = a transaction is underway on the i 2 c bus. i2cstate_h?i 2 c state this field defines the current state of the i 2 c controller. it is the most significant nibble of the internal state machine. table 115 on page 233 defines the states for this field. i2cstate_l ?least significant nibble of the i 2 c state machine. this field defines the substates for the states defined by i2cstate_h. table 116 on page 234 defines the values for this field. table 114. i 2 c state register (i2cstate) - description when diag = 1 bits 7 6 5 4 3 2 1 0 field i2cstate_h i2cstate_l reset 00000000 r/w rrrrrrrr addr ff-e245h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 233 table 115. i2cstate_h state encoding state name state description 0000 idle i 2 c bus is idle or i 2 c controller is disabled. 0001 slave start i 2 c controller has receiv ed a start condition. 0010 slave bystander address did not match - ignore remainder of transaction. 0011 slave wait waiting for stop or restart condition after sending a not acknowledge instruction. 0100 master stop2 master completing stop condition (scl = 1, sda = 1). 0101 master start/restart master mode sending start condition (scl = 1, sda = 0). 0110 master stop1 master initiating stop cond ition (scl = 1, sda = 0). 0111 master wait master received a not acknow ledge instruct ion, waiting for software to assert st op or start control bits. 1000 slave transmit data nine substates, one for each data bit and one for the acknowledge. 1001 slave receive data nine substates, one for each data bit and one for the acknowledge. 1010 slave receive addr1 slave receiving first address byte (7 and 10 bit addressing) nine substates, one for each address bit and one for the acknowledge. 1011 slave receive addr2 slave receiving second address byte (10 bit addressing) nine substates, one for each address bit and one for the acknowledge. 1100 master transmit data nine substates, one for each data bit and one for the acknowledge. 1101 master receive data nine substates, one for each data bit and one for the acknowledge. 1110 master transmit addr1 master sending first address byte (7- and 10-bit addressing) nine substates, one for each address bit and one for the acknowledge. 1111 master transmit addr2 master sending second address byte (10-bit addressing) nine substates, one for each address bit and one for the acknowledge. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 234 i 2 c mode register the i 2 c mode register (see table 117 ) provides control over master versus slave operating mode, slave address and diagnostic modes. table 116. i2cstate_l state i2cstate_h sub-state i2cstate_l sub-state name state description 0000?0100 0000 ? there are no substates for these i2cstate_h values. 0110?0111 0000 ? there are no substates for these i2cstate_h values. 0101 0000 master start initiating a new transaction. 0001 master restart master is ending one transaction and starting a new one without letting the bus go non-active. 1000?1111 0111 send/receive bit 7 sending/receiving most significant bit. 0110 send/receive bit 6 0101 send/receive bit 5 0100 send/receive bit 4 0011 send/receive bit 3 0010 send/receive bit 2 0001 send/receive bit 1 0000 send/receive bit 0 sending/receiving least significant bit 1000 send/receive acknowledge sending/receiving acknowledge table 117. i 2 c mode register (i2cmode) bits 7 6 5 4 3 2 1 0 field dmaif mode[1:0] ir m gce sla[9:8] diag reset 000000 r/w r/w r/w r/w r/w r/w r/w addr ff-e246h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 235 dmaif - dma interface mode. 0 = used when software polling or interrupts are used to move data. 1 = used when the dma is used to move data. the tdre and rdrf bits in the status register are not affected but the i 2 c interrupt is not asserted when tdre or rdrf are set. the i 2 c interrupt reflects only the error conditions. the assertion of tdre causes a transmit dma request. the assertion of rdrf causes a receive dma request. mode?selects the i 2 c controller operational mode 00 = master/slave capable (supports multi-m aster arbitration) with 7-bit slave address 01 = master/slave capable (supports multi-mast er arbitration) with 10-bit slave address 10 = slave only capable with 7-bit address 11 = slave only capable with 10-bit address irm?interactive receive mode valid in slave mode when software needs to interpret each r eceived byte before acknowledging. this bit is useful for processi ng the data bytes following a general call address or if software wants to disable hardware address recognition. 0 = acknowledge occurs auto matically and is determin ed by the value of the nak bit of the i2cctl register. 1 = a receive interrupt is generated for each by te received (address or data). the scl is held low during the acknowle dge cycle until software writes to the i2cctl register. the value written to the nak bit of the i2cctl register is out put on sda. this value allows software to acknowledge or not acknowledge after interpreting the associated address/ data byte. gce?general call address enable enables reception of messages beginning with the general call address or start byte. 0 = do not accept a message with the general call address or start byte. 1 = do accept a message with the general call address or start byte. when an address match occurs, the gca an d rd bits in the i 2 c status register indicates whether the address matched the general call address/start byte or not. following the general call address byte, software sets the irm bit that allows software to examine the following data byte(s) before acknowledging. sla[9:8]? slave address bits 9 and 8 initialize with the appropriate slave address value when using 10-b it slave addressing. these bits are ignored when using 7-bit slave addressing. diag?diagnostic mode selects read back value of the baud rate reload and state registers. 0 = reading the baud rate registers returns the baud rate register values. reading the state register returns i 2 c controller state information. 1 = reading the baud rate registers returns th e current value of the baud rate counter. reading the state register retu rns additional st ate information. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 236 i 2 c slave address register the i 2 c slave address register (see table 118 ) provides control over the lower order address bits used in 7-bit and 10-bit slave address recognition. sla[7:0] ?slave address bits 7-0. initialize with the appropriate slave address value. when using 7 bit slave addressing, sla[9:7] are ignored. table 118. i 2 c slave address register (i2cslvad) bits 7 6 5 4 3 2 1 0 field sla[7:0] reset 00h r/w r/w addr ff-e247h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 237 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y i 2 c master/slave controller zneo ? Z16F series product specification 238 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y watchdog timer zneo ? Z16F series product specification 239 watchdog timer the watchdog timer (wdt) helps protect agai nst corrupt or unreliable software, power faults, and other system-level problems which places the zneo ? Z16F series device into unsuitable operating states. the wdt includes the following features: ? on-chip rc oscillator. ? a selectable time-out response: s hort reset or system exception. ? 16-bit programmable time-out value. operation the wdt is a retriggerable one-shot timer that resets or interrupts the zneo Z16F series device, when the wdt reaches its terminal count. the wdt uses its own dedicated on-chip rc oscillator as its clock source. th e wdt has only two modes of operation?on and off. once enabled, it always counts and must be refreshed to prevent a time-out. an enable is performed by executing the wdt instruction or by setting the wdt_ao option bit. the wdt_ao bit enables the wdt to oper ate all the time, even if a wdt instruction has not been executed. to minimize power consumption, the rc os cillator is disabled. the rc oscillator is disabled by clearing the wdten bit in the oscillator control register . if the rc oscillator is disabled, the wdt will not operate. the wdt is a 16-bit reloadable downcounter that uses two 8-bit registers in the zneo cpu register space to set the reload value. the nominal wdt time-out period is given by the following equation: where, wdt reload value is the decimal valu e of the 16-bit value given by {wdth[7:0], wdtl[7:0]} and the typical watchdog time r rc oscillator frequency is 10 khz. table 119 on page 240 provides information on approximate time-out delays for the minimum, default, and maximum wdt reload values. wdt time-out period (ms) wdt reload value 10 ----------------- ------------------ -------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y watchdog timer zneo ? Z16F series product specification 240 watchdog timer refresh when enabled first, the wdt is loaded with the value in the watchdog timer reload registers. the wdt then counts down to 0000h unless a wdt instruction is executed by the zneo cpu. execution of the wdt instruction causes the do wncounter to be reloaded with the wdt reload value stored in the watchdog timer reload registers. counting resumes following th e reload operation. when the zneo Z16F series device is operating in debug mode (through the ocd), the wdt is continuously refreshed to prevent spurious wdt time-outs. watchdog timer time-out response the wdt times out when the counter reaches 0000h . a time-out of the wdt generates either a system exception or a short reset. the wdt_res option bit determines the time-out response of the wdt. for information on programming of the wdt_res option bit, see option bits on page 293. wdt system exception in normal operation if configured to generate a system exceptio n when a time-out occu rs, the wdt issues an exception request to the interrupt controller. the zneo cpu responds to the request by fetching the system exception vector and exec uting code from the vector address. after time-out and system exception generation, the wdt is reloaded automatically and continues counting. wdt system exception in stop mode if configured to generate a system exceptio n when a time-out occurs and the zneo Z16F series device is in stop mo de, the wdt automatically initia tes a stop mode recovery and generates a system ex ception request. both the wdt status bit and the stop bit in the reset status and control register are set to 1 following wdt time-out in stop mode. for detailed information, see reset and stop mode recovery on page 58. table 119. watchdog timer approximate time-out delays wdt reload value w dt reload value approximate time-out delay (with 10 khz typical wdt oscillator frequency) (hex) (decimal) typical description 0400 1024 102.4 ms reset value time-out delay ffff 65,536 6.55 s maximum time-out delay www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y watchdog timer zneo ? Z16F series product specification 241 following completion of the st op mode recovery, the zneo cpu responds to the system exception request by fetching the system ex ception vector and executing code from the vector address. wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the wdt forces the device into the reset state. the wdt status bit in the reset status and control register is set to 1. for more information on reset and the wdt status bit, see the reset and stop mode recov- ery on page 58. following a reset sequence, th e wdt counter is initia lized with its reset value. wdt reset in stop mode if enabled in stop mode and configured to ge nerate a reset when a time-out occurs and the device is in stop mode , the wdt initiates a stop mode recovery. both the wdt status bit and the stop bit in the reset status and control register register are set to 1 following wdt time-out in stop mo de. for detailed information, see reset and stop mode recovery on page 58. watchdog timer relo ad unlock sequence writing the unlock sequence to the watchdog timer reload high (wdth) register address unlocks the two watchdog timer reload registers (wdth, and wdtl) to allow changes to the time-out period. these write op erations to the wdth register address pro- duce no effect on the bits in the wdth regi ster. the locking mechanism prevents spurious writes to the reload registers. the following sequence is requ ired to unlock the watchd og timer reload registers (wdth and wdtl) for write access: 1. write 55h to the watchdog timer reload high register (wdth). 2. write aah to the watchdog timer reload high register (wdth). 3. write the appropriate value to the watc hdog timer reload high register (wdth). 4. write the appropriate value to the watc hdog timer reload low register (wdtl). all steps of the wdt reload un lock sequence must be written in the order just listed. the value in the watchdog timer reload register s is loaded into th e counter every time a wdt instruction is executed. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y watchdog timer zneo ? Z16F series product specification 242 watchdog timer regi ster definitions watchdog timer reload high and low byte registers the watchdog timer reload high and lo w byte (wdth, wdtl) registers (see table 120 through table 121 ) form the 16-bit reload value that is loaded into the wdt when a wdt instruction executes. the 16 -bit reload value is {wdth[ 7:0], wdtl[7:0]}. writing to these registers following the unlock sequence sets the appropriate re load value. reading from these registers returns the current wdt count value. the 16-bit wdt reload value must not be set to a value less than 0004h . wdth?wdt reload high byte most significant byte (msb), bits[ 15:8], of the 16-bit wdt reload value. wdtl?wdt reload low least significant byte (lsb), bits[7 :0], of the 16-bit wdt reload value. table 120. watchdog timer reload high byte register (wdth) bits 7 6 5 4 3 2 1 0 field wdth reset 00000100 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff_e042h r/w* - read returns the current wdt count value. write sets the appropriate reload value. table 121. watchdog timer reload low byte register (wdtl) bits 7 6 5 4 3 2 1 0 field wdtl reset 00000000 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff_e043h r/w* - read returns the current wdt count value. write sets the appropriate reload value. caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 243 analog functions the zneo ? Z16F series devices include a 12-channel analog-to-digital converter (adc), an operational amp lifier, and a comparator. the features of the analog functions include: ? adc with 12 analog input sources multip lexed with general-purpose input/output (gpio) ports. ? operational amplifier with output internally connect to the adc. ? comparator with separate inputs or sh ared with the operational amplifier. figure 51 displays the block diagram for analog functions. figure 51. analog functions block diagram analog-to-digital converter0 ana0 ana1 ana2 ana3 ana4 ana5 ana6 ana7 analog input multiplexer anain0[3:0] internal voltage reference generator analog input reference input s&h amp data output0 10 vref rbuf refen sample/hold0 start0 adclk adcen0 busy0 ana8 ana9 ana10 ana11 comp op-amp + - + - cinp cinn opinn compout sample/hold1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 244 adc overview the zneo Z16F series devices include a 12 -channel adc. the adc converts an analog input signal to a 10-bit binary number. the features of the successive approximation adc include: ? 12 analog input sources mu ltiplexed with gpio ports. ? fast conversion time (2.5 s). ? programmable timing controls. ? interrupt on conversion complete. ? internal voltage reference generator. ? internal reference voltage available externally. ? ability to supply extern al reference voltage. ? ability to do simultaneous or independent conversions. architecture the architecture as illustrated in figure 51 on page 243 consists of an 12-input multi- plexer, sample-and-hold amplifier, and 10 -bit successive approximation adc. the adc digitizes the signal on selected channel and stores the digitized data in the adc data regis- ters. in environment with high electrical noise, an external rc filter must be added at the input pins to reduce high frequency noise. operation the adc converts the analog input, ana x , to a 10-bit digital representation. the equation for calculating the di gital value is represented by: assuming zero gain and offset errors, any vo ltage outside the adc input limits of avss and vref returns all 0s or 1s, respectively. a new conversion is initiated by either soft ware write to the adc control register?s start bit or by pwm trigger. for detaile d information on the pwm trigger, see synchronization of pwm and adc on page 120. initiating a new conversion stops any conversion currently in progress and begins a new conversion. to avoid disrupting a conversion already in progress, the start bit is read to indicate adc operation status (busy or available). adc output = 1024*(anax/vref) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 245 adc timing each adc measurement consists of three phases: 1. input sampling (programmable, minimum of 1.0 s). 2. sample-and-hold amplifier settlin g (programmable, minimum of 0.5 s). 3. conversion is 12 adclk cycles. figure 52 displays the timing of an adc conversion. figure 52. adc timing diagram figure 53 displays the timing of convert period sh owing the 10 bit progression of the out- put. figure 53. adc convert timing start bit sample/hold 1.0 us min sample period programable settling period busy 12 clock convert period conversion period set by user cleared by busy internal signal internal signal busy 12 clocks convert period adc clock 12345678910111213141516 17 convertbit5 convertbit4 convertbit3 convertbit2 convertbit1 convertbit0 and store convertbit 8 convertbit7 convertbit6 convert msb www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 246 adc interrupts the adc generates an interrupt request when a conversion has been completed. an interrupt request pending when the adc is disabled is not automatically cleared. adc0 timer0 capture the timer0 count is captured for every adc0 conversion. the information is used to determine the zero crossing of back emf in mo tor control applications . the capture of the timer0 count occurs when the programmed samp le time is complete for every conversion and stored in the adc timer capture register (adctcap). adc convert on read the adc is set up to automatically convert th e next channel input after reading the results of the current conversion. the conversions continue up to the channel listed in the adc0max register and then start over at th e initial channel. the initial channel to con- vert is written to the control register, adc0c tl, prior to starting the convert on read process. once started, the conversions contin ue to loop from the initial channel to max channel until the conv ert on read bit, cvtrd0 , is cleared or the data is not read from the data registers. reference buffer, rbuf the reference buffer, rbuf, supplies the refe rence voltage for the adc. when enabled, the internal voltage reference generator supp lies the adc and the voltage is available on the vref pin. when rbuf is disabled, the refe rence voltage must be supplied externally through the vref pin. rbuf is controlled by the refen bit in the adc0 control register. internal voltage reference generator the internal voltage referen ce generator provides the volta ge to rbuf. the internal reference voltage is 2 v. adc control register definitions the following sections describe th e control registers for the adc. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 247 adc0 control register 0 the adc0 control register initiates the a/ d conversion and provides adc0 status information. table 122. adc0 control register 0 (adc0ctl) bits 7 6 5 4 3 2 1 0 field start0 cvtrd0 refen adc0en anain0[3:0] reset 00000000 r/w r/w1 r/w r/w r/w r/w r/w r/w r/w addr ff-e500h bit position value (h) description [7] start0 0 adc0 start / busy writing to 0 has no effect. reading a 0 indicates the adc0 is available to begin a conversion. 1 writing to 1 starts a conversion on adc0. reading a 1 indicates a conversion is currently in progress. [6] cvtrd0 0 convert on read the adc0 operates normally. 1 if this bit is set to one, whenever the ad c0d register is read it increments the anain field by one and start a new conversion. the anain field increments until it reaches the value set in the adc0max register. after doing the conversion on the channel specified by the adc0max register, the next read resets the anain field to zero. this fu nction is used with the dma to perform continuous conversions. [5] refen 0 reference enable internal reference voltage is disabled allowing an external reference voltage to be used by the adc0. 1 internal reference voltage for the adc0 is enabled. the internal reference voltage is measured on the vref pin. [4] adc0en 0 adc0 enable adc0 is disabled for low power operation. 1 adc0 is enabled for normal use. [3:0] anain0 0000 analog input select ana0 input is selected for analog-to-digital conversion. 0001 ana1 input is selected for analog-to-digital conversion. 0010 ana2 input is selected for analog-to-digital conversion. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 248 adc0 data high byte register the adc0 data high byte register contains the upper eight bits of the adc0 output. access to the adc0 data high byte register is read-only. 0011 ana3 input is selected for analog-to-digital conversion. 0100 ana4 input is selected for analog-to-digital conversion. 0101 ana5 input is selected for analog-to-digital conversion. 0110 ana6 input is selected for analog-to-digital conversion. 0111 ana7 input is selected for analog-to-digital conversion. 1000 ana8 input is selected for analog-to-digital conversion. 1001 ana9 input is selected for analog-to-digital conversion. 1010 ana10 input is selected for analog-to-digital conversion. 1011 ana11 input is selected for analog-to-digital conversion. 1100 to 1111 reserved table 123. adc0 data high byte register (adc0d_h) bits 7 6 5 4 3 2 1 0 field adc0d_h reset x r/w r addr ff-e502h bit position value (h) description [7:0] 00h?ffh adc0 high byte the last conversion output is held in the data registers until the next adc conversion is completed. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 249 adc0 data low bits register the adc0 data low bits register contains the lower bits of the adc0 output. access to the adc0 data low bits re gister is read-only. sample settling time register the sample settling time register is used to program the length of time from the sample/ hold signal to the start signal, when the conversion begins. the number of clock cycles required for settling varies from system to system depending on the system clock period used. you must program this register to contain the number of clocks required to meet a 0.5 s minimum settling time. table 124. adc0 data low bits register (adc0d_l) bits 7 6 5 4 3 2 1 0 field adc0d_l reserved reset xx r/w rr addr ff-e503h bit position value (h) description [7:6] 00?11b adc0 low bits these bits are the 2 least significant bits of the 10-bit adc0 output. these bits are undefined after a reset. [5:0] reserved 0 reserved?must be 0. table 125. sample and settling time (adcsst) bits 7 6 5 4 3 2 1 0 field reserved sst reset 00011111 r/w rr/w addr ff-e504h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 250 sample time register the sample time register is used to program the length of active time for the sample once a conversion has begun by setting the start bit in the adc control register or initiated by the pwm. the number of system clock cy cles required for sample time varies from system to system depending on the clock peri od used. you must program this register to contain the number of system clocks required to meet a 1 s minimum sample time. bit position value (h) description [7:5] 0h reserved?must be 0. [4:0] sst 00h -1fh sample settling time sample settling time in number of system clock periods to meet 0.5 s minimum. table 126. sample time (adcst) bits 7 6 5 4 3 2 1 0 field reserved st reset 0 111111 r/w rr/w addr ff-e505h bit position value (h) description [7:6] 0h reserved?must be 0. [5:0] sht 00h - 3fh sample hold time sample hold time in number of system clock periods to meet 1 s minimum. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 251 adc clock prescale register the adc clock prescale register is used to provide a divided system clock to the adc. when this register is progra mmed with 0h, the system clock is used for the adc clock. table 127. adc clock prescale register (adccp) bits 7 6 5 4 3 2 1 0 field reserved div16 div8 div4 div2 reset 00000 r/w rr/w addr ff-e506h bit position value (h) description [7:4] 0h reserved?must be 0. [3] div16 0 div16 clock is not divided. 1 system clock is divided by 16 for adc clock. [2] div8 0 div8 clock is not divided. 1 system clock is divided by 8 for adc clock. [1] div4 0 div4 clock is not divided. 1 system clock is divided by 4 for adc clock. [0] div2 0 div2 clock is not divided. 1 system clock is divided by 2 for adc clock. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 252 adc0 max register the adc0 max register. this register determ ines the highest channel that the convert on read increments too. adc timer0 capture register the adc timer0 capture register contains the sixteen bits of the adc timer0 count. the access to the adc timer0 capture register is read-only. it reads 8 bits at a time or as a 16-bit word. table 128. adc0 max register (adc0max) bits 7 6 5 4 3 2 1 0 field reserved lastchan0 reset 00h r/w r/w addr ff-e507h bit position value (h) description [7:4] 0h reserved - must be 0. [3:0] lastchan0 0 last channel0 these bits determine the last channel number to increment to when the convert on read is set. table 129. adc timer0 capture register, high byte (adctcap_h) bits 7 6 5 4 3 2 1 0 field adctcaph reset x r/w r addr ff-e512h bit position value (h) description [7:0] 00h?ffh adc timer0 count high byte the timer0 count is held in the data registers until the next adc conversion is started. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 253 comparator and operational amplifier overview the zneo devices feature a general-purpose co mparator and an operational amplifier. the comparator is a moderate speed (200 ns propagation delay) device which is designed for a maximum input offset of 5 mv. the compar ator is used to compare two analog input signals. general-purpose input pins (cinp and cinn) provides the comparator inputs. the output is available as an interrupt source. the operational amplifier is a two-input, one-output operati onal amplifier with a typical open loop gain of 10,000 (80 db). the general-purpose input pin (opinp) provides the non-inverting amplifier input, while gene ral-purpose input pin (opinn) provides the inverting amplifier input. the output is available at the output pin (opout). the key operating characteristics of the operational amplifier are: ? frequency compensated fo r unity gain stability. ? input common-mode-range from gnd (0.0 v) to vdd ? 1 v. ? input offset voltage less than 15 mv. ? output voltage swing from gnd + 0.1 v to v dd ? 0.1 v. ? input bias current less than 1 a. ? operating the operational am plifier open loop (no feedback) effectively provides another on-chip comparator. table 130. adc timer0 capture register, low byte (adctcap_l) bits 7 6 5 4 3 2 1 0 field adctcapl reset x r/w r addr ff-e513h bit position value (h) description [7:0] 00h - ffh adc timer0 count low byte the timer0 count is held in the data r egisters until the next adc conversion is started. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 254 comparator operation the comparator output reflects the relation ship between the non-in verting input and the inverting (reference) input. if the voltage on the non-inverting inpu t is higher than the voltage on the inverting input, the comparator outp ut is at a high state. if the voltage on the non-inverting input is lower than the voltage on the inverting input, the comparator output is at a low state. to operate, the comparator mu st be enabled by setting the cmpen bit in the comparator and op-amp register to 1. in addition th e cinp and cinn comparator input alternate functions must be enabled on their respec tive gpio pins. for mo re information, see gpio alternate functions on page 69. the comparator does not automatically powe r-down. to reduce ope rating current when not in use, the comparator is disabled by clearing the cmpen bit to 0. operational amplifier operation to operate, the operational amplif ier must be enabled by setting the open bit in the comparator and op-amp register to 1. in addition, the opinp, opinn, and opout alter- nate functions must be enab led on their respective genera l-purpose i/o pins. for more information, see gpio alternate functions on page 69. the logical value of the operational amplifier output (opout) is read from the port 3 data input register if both the operational amplif ier and input pin schmit t trigger are enabled. for more information, see gpio alternate functions on page 69. the operational ampli- fier generates an interrupt via the gpio port b3 input interrupt, if enabled. the output of the operational amplifier is also connected to an analog input (ana3) of the adc multiplexer. the operational amplif ier does not automatically powe r-down. to reduce operating cur- rent when not in use, the operational amplifier is disabled by clearing the open bit in the comparator and op-amp register to 0. when the operational amplif ier is disabled, the output is high impedance. interrupts the comparator generates an in terrupt on any change in the logic output value (from 0 to 1 and from 1 to 0). for information on enab ling and prioritization of the comparator interrupt, see interrupt controller on page 80. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 255 comparator control register definitions the following sections describe th e comparator control registers. comparator and operational amplifier control register the comparator and operatio nal amplifier control register (cmpopc) enables the comparator and operational amplifier and provides access to the comparator output. table 131. comparator and op amp control register (cmpopc) bits 7 6 5 4 3 2 1 0 field open reserved cpisel cmpirq cmpiv cmpout cmpen reset 000000x0 r/w r/w r r/w r/w r/w r r/w addr ff_e510h bit position value (h) description [7] open 0 operational amplifier disable operational amplifier is disabled. 1 operational amplifier is enabled. [6:5] reserved must be 0. [4] cpisel 0 comparator input select portb6 provides the comparator - input. 1 portc0 provides the comparator - input. [3] cmpirq 0 comparator interrupt edge select interrupt request on comparator rising edge. 1 interrupt request on co mparator falling edge. [2] cmpiv 0 pwm fault comparator polarity pwm fault is active when cp+ > cp- 1 pwm fault is active when cp- > cp+ [1] cmpout 0 comparator output value comparator output is logical 0. 1 comparator output is logical 1. [0] cmpen 0 comparator enable comparator is disabled. 1 comparator is enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y analog functions zneo ? Z16F series product specification 256 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 257 flash memory the products in the zneo ? Z16F series feature up to 128 kb of non-volatile flash memory with read/wri te/erase capability. the flash memo ry is programmed and erased in-circuit by either user code or through the ocd. the flash memory array is arra nged in 2 kb pages. the 2 kb page is the minimum flash block size that is erased. the flash memory is also divided into eight sectors, which is protected from programming and erase operations on a per sector basis. table 132 describes the flash memory configura tion for each device in the zneo Z16F series. table 133 lists the sector address ranges. figure 54 on page 258 displays the flash memory arrangement. table 132. flash memory configurations part number internal flash size number of pages program memory addresses sector size number of sectors pages per sector Z16F2811 128 kb 64 000000h - 01ffffh 16 kb 8 8 Z16F2810 128 kb 64 000000h - 01ffffh 16 kb 8 8 Z16F6411 64 kb 32 0000h - ffffh 8 kb 8 4 Z16F3211 32 kb 16 0000h - 7fffh 4 kb 8 2 table 133. flash memory sector addresses sector number flash sector address ranges Z16F2811/Z16F2810 Z16F6411 Z16F3211 0 000000h - 003fffh 000000h - 001fffh 000000h - 000fffh 1 004000h - 007fffh 002000h - 003fffh 001000h - 001fffh 2 008000h - 00bfffh 004000h - 005fffh 002000h - 002fffh 3 00c000h - 00ffffh 006000h - 007fffh 003000h - 003fffh 4 010000h - 013fffh 008000h - 009fffh 004000h - 004fffh 5 014000h - 017fffh 00a000h - 00bfffh 005000h - 005fffh 6 018000h - 01bfffh 00c000h - 00dfffh 006000h - 006fffh 7 01c000h - 01ffffh 00e000h - 00ffffh 007000h - 007fffh www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 258 figure 54. flash memory arrangement information area table 134 on page 259 describes the zneo Z16F series information area. this 128-byte information area is accessed by setting bit 7 of the flash control register to 1. when access is enabled, the information area is ma pped into program memory and overlays the 128 bytes at addresses 000000h to 00007f h. when the information area access is enabled, instructions access da ta from the information area. the cpu instruction fetches always come from main memory regardless of the informa tion area access bit. access to the information area is read-only. 128 kb flash program memory 000000h 64 pages 2 kb per page 0007ffh 000800h 000fffh 01f000h 01f7ffh 01f800h 01ffffh 001000h 0017ffh 01e800h 01efffh addresses www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 259 operation the flash controller provides the proper signals and timing for word programming, page erase, and mass erase of the flash memory. the flash controller contains a protection mechanism, using the flash command re gister (fcmd), to prevent accidental programming or erasure. the following su bsections provide details on the various operations (lock, unlock, sector protect, byte programming, page erase, and mass erase). timing using the flash frequency register before performing a program or erase operat ion on the flash memory, you must first configure the flash frequency register. the flash frequency register allows programming and erasure of the flash with system clock frequencies ranging from 32 khz through 20 mhz (the valid range is limited to the device operating frequencies). the 16-bit flash frequency register must be written with the system clock frequency in khz before a program or erase operation is initiated. this va lue is calculated using the following equation: flash programming and erasure is not su pported for system clock frequencies below 32 khz, above 20 mhz, or outside of the device operating frequency range. the flash frequency register must be loaded with the correct value to ensure prop - er flash programming and erase operations. flash read protection the user code within the flash memory is protected from external access. programming the flash read protect option b it prevents reading of user code by the table 134. zneo Z16F series information area map program memory address (hex) function 000000h-00003fh reserved. 000040h-000053h part number 20-character ascii alphanumeric code left justified and padded with zeros. 000054h-00007fh reserved. ffreq[15:0] system clock frequency (hz) 1000 --------------------- --------------------- ----------------- ----------------- = caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 260 ocd or by using the flash controller byp ass mode. for more information, see option bits on page 293 and on-chip debugger on page 299. flash write/erase protection the zneo Z16F series provides several levels of protection against accidental program and erasure of the flash memory contents. this protection is provided by the flash controller unlock mechanism, the flash sector protect register, and the flash write protect option bit. flash controller unlock mechanism at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory , the flash controller must be unlocked. after unlocking the flash controller, the fl ash is programmed or erased. any value written by user code to the fl ash command register or flash page select register out of sequence locks the flash controller. follow the steps below to unlock th e flash controller from user code: 1. write the page to be programmed or er ased to the flash page select register. 2. write the first unlock command 73h to the flash command register. 3. write the second unlock command 8ch to the flash command register. flash sector protection the flash sector protect register is config ured to prevent sectors from being programmed or erased. once a sector is protected, it cannot be unprotected by user code. the flash sec- tor protect register is cleared after reset an d any previously written protection values will be lost. user code must write this register in their initialization routine if they want to enable sector protection. when user code writes the flash sector protect register, bits are set to 1 only. thus, sectors are protected, but not unprotected, using register write operations. flash write protection option bit the flash write protect option bit is enabled to block all program and erase operations from user code. for detailed information, see option bits on page 293. programming when the flash controller is unlocked, word writes to program memory from user code programs a word into the flash if the address is located in the unlocked page. an erased flash word contains all ones ( ffffh ). the programming operation is used to change bits from one to zero. to change a flash bit (or mu ltiple bits) from zero to one requires a page erase or mass erase operation. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 261 the flash must be programmed one word (16- bits) at a time. if a byte (8-bit) write to flash memory occurs, the flash controller wa its until the other byte within the word is written before beginning th e programming operation. while the flash controller programs the flash memory, flash reads are held in wait. if the cpu is fetching instruction from flash, the cpu idles until the programming operation is complete. interrupts that occur when a prog ramming operation is in progress are serviced once the programming operation is complete . to exit programming mode and lock the flash controller, write 00h to the flash command register. user code cannot program flash memory on a page that lies in a protected sector. when user code writes memory locations, only ad dresses located in the unlocked page are programmed. memory writes outside of the unlocked page are ignored. each memory location must not be prog rammed more than twice before an erase occurs. follow the steps below to program the flash from user code: 1. write the page of memory to be programmed to the flash page select register. 2. write the first unlock command 73h to the flash command register. 3. write the second unlock command 8ch to the flash command register. 4. write a word to program memory. 5. repeat step 4 to program additional memory locations on the same page. 6. write 00h to the flash command register to lock the flash controller. page erase the flash memory is erased one page (2 kb ) at a time. page erasing the flash memory sets all words in that page to the value ffffh . the flash page select register identifies the page to be erased. while the flash contro ller executes the page erase operation, flash reads are held in wait. interrupts that occur when the page erase operation is in progress will be serviced once the page erase operation is complete. when the page erase opera- tion is complete, the flash cont roller returns to its locked st ate. only pages located in unprotected sectors are erased. the steps to perform a page erase operation are: 1. write the page to be erased to the flash page select register. 2. write the first unlock command 73h to the flash command register. 3. write the second unlock command 8ch to the flash command register. 4. write the page erase command 95h to the flash command register. caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 262 mass erase the flash memory cannot be mass erased by user code. flash controller bypass the flash controller is bypassed and the contro l signals for the flash memory brought out to the gpio pins. bypassing the flash contro ller allows faster programming algorithms by controlling the flash programming signals directly. flash controller bypass is recommended for large volume gang programming applications, which do not require in-c ircuit programming of the flash memory. flash controller behavior using the on-chip debugger the following changes in behavior of th e flash controller occur when the flash controller is accessed us ing the on-chip debugger: ? the flash controller does not have to be unlocked for program and erase operations. ? the flash write protect option bit is ignored. ? the flash sector protect register is igno red for programming and erase operations. ? programming operations are not limited to th e page selected in the flash page select register. ? bits in the flash sector protect register is written to one or zero. ? the flash page select register is writte n when the flash cont roller is unlocked. ? the mass erase command is enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 263 flash control register definitions flash command register the flash command register (see table 135 ) unlocks the flash controller for program- ming and erase operations. the write-only fl ash command register shares its address with the read-only flash status register. fcmd?flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command. 63h = mass erase command. * all other commands, or any command out of sequence locks the flash controller. flash status register the flash status register (see table 136 ) indicates the current stat e of the flash controller. this register is read at any time. the read-only flash status register shares its address with the write-only flash command register. unlock?unlocked this status bit is set when th e flash controller is unlocked. table 135. flash command register (fcmd) bits 7 6 5 4 3 2 1 0 field fcmd reset xxh r/w w addr ff_e060h table 136. flash status register (fstat) bits 7 6 5 4 3 2 1 0 field unlock reserved fstat reset 00 00h r/w rr r addr ff_e060h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 264 0 = flash controller locked. 1 = flash controller unlocked. reserved this bit is reserved and is 0. fstat?flash controller status 00_0000 = flash controller idle. 00_1xxx = program operation in progress. 01_0xxx = page erase operation in progress. 10_0xxx = mass erase operation in progress. flash control register the flash control register selects how the flash memory is accessed. info?information area access this bit selects access to the information area. 0 = information area is not selected. 1 = information area is selected. the inform ation area is mapped into the program mem- ory address space at addresses 000000h through 00007fh . reserved these bits are reserved and must be written to zero. table 137. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field info reserved reset 0 00h r/w r/w r addr ff_e061h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 265 flash sector protect register the flash sector protect register (see table 138 ) protects flash memory sectors from being programmed or erased from user code. user code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code). sect n ?sector protect 0 = sector n is programmed or erased from user code. 1 = sector n is protected and cannot be prog rammed or erased from user code. * user code write bits from 0 to 1 only. flash page select register the flash page select (fpage) register (see table 139 ) selects one of the 64 available flash memory pages to be erased or program med. each flash page contains 2048 words of flash memory. during a page erase opera tion, all flash memory locations within the page will be erased to ffffh . reserved these bits are reserved and are 0. table 138. flash sector protect register (fsect) bits 7 6 5 4 3 2 1 0 field sect7 sect6 sect5 sect4 sect3 sect2 sect1 sect0 reset 00000000 r/w r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 addr ff_e062h r/w1 = register is accessible for read operations. register is written to 1 only (via user code). table 139. flash page select register (fpage) bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field reserved page reserved reset 00h 00h 0h r/w rr/wr addr ff_e064-ff_e065h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y flash memory zneo ? Z16F series product specification 266 page?page select this 6-bit field selects the flash memory page for programming and page erase operations. program memory addre ss[16:11] = fpage[8:3] = page[5:0]. flash frequency register the flash frequency register (see table 140 ) sets the time for flash program and erase operations. the 16-bit flash frequency regist er must be written with the system clock frequency in khz. the flash frequency value is calculated using the following equation: flash pr ogramming and erasure is not supporte d for system clock frequencies below 32 khz, above 20 mhz, or outside of the valid operating frequency range for the device. the flash frequency register must be loaded with the correct value to ensure pr oper program and erase times. ffreq?flash frequency this value is used to time flas h program and erase operations. table 140. flash frequency register (ffreq) bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field ffreq reset 0000h r/w r/w addr ff_e066-ffe067h ffreq[15:0] system clock frequency 1000 ------------------ ------------------ ----------------- ---------- = caution: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 267 dma controller the four dma channels are u sed to transfer data from memory to memory, memory to peripherals, peripherals to memory , or peripherals to peripherals. dma features the features of dma controller include: ? four independent dma channels. ? memory<=>memory, memory<=>perip heral, peripheral<=>memory, peripheral<=>peripheral transfers. ? direct or linked list modes of operation. ? byte, word, or quad operation. ? dma and cpu bandwidth sharing control. ? up to 64 k transfers (64 kbyte, 64 kword or 64 kquad). ? external dma request and dma acknowledge signals. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 268 dma block diagram figure 55. dma block diagram channel memory bus dma bus controller mux channel 0 request0 request eof0 acknowledge0 interrupt0 channel 1 request1 request eof1 acknowledge1 interrupt1 channel 2 request2 request eof2 acknowledge2 interrupt2 channel 3 request3 request eof3 acknowledge3 interrupt3 cmdvld eofsync rdstat cmdbus statbus (internal only) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 269 dma description the dma is used to off load the processor from doing repetitive ta sks. dma transfers data from one memory address to another memory address. since all peripherals are mapped in memory, the dma transfers data to or from peripherals. the dma transfers data from the source address to the destination address. this requires a read and/or write cycle that is generated by the dma controller. each dma transfer requires a minimum of two system clock cycles to execute. the dma operates in direct or linked list m ode. direct mode and linked list mode are almost the same. in direct mode the software loads the dma channel registers directly. in linked list mode the dma loads its registers from memory. dma register description each dma channel consists of 16-bit control re gister, a 16-bit transfer length register, a 24-bit destination address register, a 24-bit sour ce address register and a 24-bit list address register (see figure 56 ). buffers a buffer is an allocation of contiguous memory bytes. buffers are allocated by software to be used by the dma. the dma transfers data to or from buffers. a typical application would be to send data to serial channels such as i 2 c, uart, and spi. the data to be sent is placed in a buffer by software. figure 56. dma channel registers dma control (dmactl) transfer length (txln) destination address (dar) source address (sar) list address (lar) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 270 frames a frame is a single buffer or a collection of buffers. frame boundaries spans multiple buffers. source address register the source address register (sar) points to the da ta to be transferred. each time a transfer occurs the sar is selected to stay fixed or increment/decrement by the size of the transfer (example 1, 2, 4). if we were sending data to a serial channel, the sar points to the data to be transferred and the sar would be set to increment or decrement depending on the order of data in the buffer (ascending or desending). destination address register the destination address register (dar) points to the location to store the data transferred from the address pointed to by the sar. each time a transfer occurs the dar is selected to stay fixed or increment/decrement by the size of the transfer (for example, 1, 2, and 4). when sending data to a serial channel, the dar points to the data register of the serial channel and is set to a fixed address. each tran sfer is then sent to the serial channel data register since the dar would not change. transfer length the transfer length register (txln) is used to specify how many transfers need to occur to transfer this buffer. if we were sending bytes to a serial channel, the value of the number of bytes in the buffer pointed to by the sar wo uld be placed in this register. each time a transfer takes place this re gister is decremented by one. when the transfer length decrements to zero, the buffer is complete an d the dma either stops or loads new control information and addresses (see linked list description). list address register the list address register (lar) is only used for linked list mode. the lar points to a list of descriptors (described below). this descrip tor list contains setup information for each buffer the dma is to transfer. linked list dmas reduce the amount of overhead on the cpu to service the dma. descriptor a descriptor is a 16 byte field in the memory space. it needs to be aligned on 16 byte boundaries (that is lower 4-bits of address is 0). table 141 provides the descriptor format. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 271 dma control bit definitions the following paragraphs explain the control bits of each dma channel. dmaxen this bit if set by the cpu en ables the dma channel for direct operation. direct operation uses the addresses and transfer length, whic h has been directly written to the dma channel by software. if this bit is set by a descriptor read then lin ked list mode is enabled. linked list operation starts when an address is written to the dmax lar. this write causes the dma to read in the descriptor control value and address es and place them in the dma channel. loop if the dma is in linked list mode and this b it is set to one, it prevents the dma from updating the descriptor when the buffer is closed. this bit is set to allow lists to loop on themselves without so ftware intervention. txsize the txsize bits sets the width of the transfer. 00 = 8-bit bytes are transferred on each dma transfer. the destination and source addresses increment or decrem ent by one for each transfers if the dstctl and/or src- ctl is selected for increment or decrement. the transfer length is decremented by one. this allows 64 kbytes to be transferred. 01 = a 16-bit word is transferred on each dma transfer. the destination and source addresses increment or decrement by two if the dstctl and/or srcctl is selected for increment or decrement. in word mode the tran sfer length is still decremented by one. this allows 64 kwords to be transferred. 10 = a 32-bit quad is transferred on eac h dma transfer. the destination and source addresses increment or decrement by four if the dstctl and/or srcctl is selected for table 141. linked list descriptor address even lar control lar + 02h txln lar + 04h dar high lar + 08h sar high lar + 0ch lar high www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 272 increment or decrement. in quad mode, the tr ansfer length is still decremented by one. this allows 64 kquads to be transferred. dstctl and srcctl fields the dstctl and srcctl fields control the in crement or decrement of the source and destination addresses. the address is set to increment, decrement or not change on each dma transfer. 00 = fixed 01 = increment 10 = decrement 11 = reserved ieob (interrupt on end of buffer) the interrupt on end of buffer bit forces th e dma channel to generate an interrupt when the buffer is closed. if the dma is operating in direct mode and the txln decrements to the watermark value (see dma water mark on page 273) and this bit is set then a interrupt is also generated. txfr (transfer list) if the dma is operating in linked list mode and this bit is set, the dma uses the next lar address in the descriptor for the next descript or address instead of incrementing the current dmaxlar address by 16. this allows looping, true linked lists with buffers following the descriptor or just transfers to other loops. eof (end of frame) if this bit is set, the eof signal is sent to the peripheral on the last transfer in the buffer (that is txln == 1). this signals the peripheral to close this frame. this is only used for on chip peripherals. this bit is also set if a peripheral requests an end of frame before the buffer transfer is completed. halt (halt after this buffer) if this bit is set then the dma stops after th is buffer is closed. the dmaxlar points to the next descriptor but the descriptor will not be fetched. cmdstat (command status) these four bits are exported to the requestin g device on the cmdbus on the first transfer of a new buffer. these bits are set by a software write or from the dma reading the descriptor. at the end of a buffer these four b its will contain status from the peripheral if the eof bit is set. see periph eral devices specs for definitio ns of commands and status. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 273 dma water mark when operating in direct mode the dmaxlar[23 :16] byte is used as a water mark inter- rupt. if these bits are set to any value other than 0, they are co mpared to the low byte of the decremented transfer length during a transfer. if the ieob bit is set and the upper byte of dmaxtxln[15:8] is zero and dmaxtxln[7 :0] == dmaxlar[23:16] then an inter- rupt is generated. this functio n allows the dma channel to ge nerate an interrupt prior to the buffer becoming empty. dma peripheral interface signals the dma uses two input signals, four output signals and two 4-bit buses to communicate with the peripherals. the input signals are request (req) and request eof. the output signals are acknowledge (ack), command valid (cmdvld), end of frame (eof- sync) and read status (rdstat). the two 4-bit busses are command bus (cmdbus) and stat bus (statbus). a dma transfer is initiated with the requ est (req). when the dma is servicing a request from a peripheral it will assert its ack nowledge signal (ack) to let the peripheral know that a transfer is in progress. when th e first byte of the transfer is written the cmd- vld is asserted and the command bits are pl aced on the cmdbus. the peripheral needs to latch the command from the bus when it sees this combination of signals. if the eof bit is set on the current buffer, when the txln decrements to zero the eof- sync signal is asserted on the last data transfer to the peripheral to let it know that this is the last byte in the frame. after receiving the eofsync signal the periph eral need to assert the request eof signal to the dma to let the dma know that the desc riptor is closed. this could be immediately or at some later time if the data transferred still needs to be processed. fo r peripherals, which do not support a request eof, the eo fsync is tied to request eof to terminate the transfer. once the request eof is asserted the dma cl oses the descriptor. the dma asserts the ack and rdstat signal, if the descriptor eof bit is set. the peripheral, if it has status, places it on the statbus. this status is then placed in the descriptor and dma status bits when it is closed. if a peripheral needs to close a descriptor be cause of an error or the end of a packet is reached then it asserts it is request eof. if th e transfer length is not zero, then the dma will set the eof bit, close the desc riptor and generate an interrupt. buffer closure a dma buffer closure is requested in two wa ys. the first is when the transfer length reaches zero. the second is when the dma receives a request end of frame from the peripheral. when either of these cases occu r, the dma begins closure of the buffer. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 274 loop mode closure if the loop bit is set then the current buff er descriptor is not modified. the dmaxlar increments or a new lar value is fetched from the descriptor. eof closure the dmaxen bit is reset to zero. if the eof bit is set, the cmdstat field is set with the status data from the peripheral. if the channe l is in linked list mode then the dmaxctl word is written back to the control word of the descriptor. the dmaxlar increments or is loaded with new lar data from the descriptor if the txfr bit is set. normal closure the dmaxen bit is reset to zero. if the channel is in linked list mode then the dmaxctl word is written back to the control word of the descriptor. the dmaxlar increments or is loaded with new lar data from the descriptor if the txfr bit is set. dma modes each dma channel operates in two modes, direct and linke d list. both modes use the dma channel registers. the only difference is in how they are loaded. in direct mode the dma channel registers are directly loaded by software and when the transfer is done the dma stops. in linked list mode the dma will lo ad its own registers from a descrip- tor list which is pointed to by the dmaxlar register. it then loads the next descriptor in the list and con tinue executing. the descriptor control/status field and addre ss bytes have the same format as the control and address registers in the dma. direct mode direct mode only uses the registers in the dma for operation. the software writes these register directly to setup and enable the dma. direct mode is entered by directly setting the dmaxen bit in the dmaxctl0 register. figure 57 on page 275 displays the dma registers and how they point to the buffers allocated in memory. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 275 figure 57. direct dma diagram dma control (dmactl0,1) transfer length (txln) destination address (dar) source address (sar) list address (lar) destination buffer source buffer memory map dma channel registers www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 276 direct dma setup and operation follows the steps below to set up the dma in direct mode: 1. write the damxreqsel to select the request source. 2. write the dmaxdar register with the destination address. 3. write the dmaxsar register with the source address. 4. write the dmaxtxln with the transfer length. 5. write dmaxlaru with water mark if required, otherwise write to zero. 6. write dmaxctl. note that control regi ster and address are directly written with word and quad operations. ?dma x en, set to one. ? loop, reset to zero, not used in this mode ? txsize, set to the transfer size, byte, word or quad. ? dstctl, set to fixed, increment, or decrement. ? srcctl, set to fixed, increment, or decrement. ? ieob, set to one to generate an interrupt at the end of buffer or water mark. ? txfr, reset to zero, not used in this mode. ? eof, set this bit to one if this is an eof buffer. ? halt, reset to zero, no t used in this mode. ? cmdstat, set these bits with the command for the peripheral. 7. the dma is now set up and begins operating when it receives a request. once the dma is set up and a request is received the dma does the following: 1. generate a request to the cpu. 2. it transfers data for each request until th e transfer length reaches zero or the dma receives a request eof signal. 3. when the dma receives the request eof signa l, or the transfer length reaches zero it resets the dmaxen bit and then does the following based upon the eof and ieob bits. if eof is set then the dma reads the status from the peripheral and places it in the cmdstat field of the dmaxctl register. if the ieob bit is set or the buffer ended with a request eof the dma channe l generates a request to the cpu. if eof is not set and ieob is set then the dma channel generates a request to the cpu. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 277 linked list mode linked list mode requires the software to allo cate buffers and setup a list of descriptors for each buffer. once this is done the software writes dmaxlar with the address of the first descriptor. after the dmaxlar is written, the dma reads the first descriptor into the dma control and address registers with the exception of the lar data. it executes the transfers as specified by the descriptor data in the dma. when the transfers are complete, the dma reads in the next descriptor in the list and continue executing transfers. figure 58 on page 278 displays two descriptors and two sets of destination and source buffers. it also displays how the descriptors are loaded into the dma and then executed. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 278 figure 58. linked list diagram destination buffer 0 source buffer 0 destination buffer 1 source buffer 1 memory dma control (dmactl0,1) transfer length (txln) destination address (dar) source address (sar) list address (lar) control/status dar sar txln lar control/status dar sar txln lar txfr bit set dma channel 1 rst descriptor descriptor pointer 2 nd descriptor source pointers destination pointers www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 279 linked list setup and operation the software initially needs to create the descriptor lists and allocate the buffers for each list. in addition, software needs to do the following: 1. write the damxreqsel to select the appropriate request source. 2. set the control field in the descriptor (not the dma) for the appropriate operation: ? dmaxen, set to one ? loop, set to one to not ha ve the descriptor modified. ? txsize, set the appropriate size for byte, word or quad. ? dstctl, set this for increment, decrement, or fixed. ? srcctl, set this for increment, decrement, or fixed. ? ieob, set to one if an interrupt must be generated when this descriptor is closed. ? txfr, set this bit if the lar is u sed to point to the next descriptor. ? eof, if this is an end of frame buffer then set this bit. ? halt, if the dma must stop at the end of this buffer then set this bit to one. ? cmdstat, set this field with a command for the selected peripheral. 3. write the destination address to the destination field. 4. write the source address to the source field. 5. write the transfer length for this buffer. 6. if this descriptor has its txfr bit set then the lar addr ess to point to the next descriptor. 7. if there are additional descriptors in the lis t then set them up using the same procedure listed above. after the descriptor has been set up, the soft ware must write the dmaxlar in the appro- priate dma with the address of the d escriptor. the dma performs the following: 1. generate a request to the cpu. 2. place the dmaxlar address on the bus and fetch the control word from the descriptor. this word is then placed in the dmaxctl register of the dma channel. 3. fetch the destination address from the d escriptor and place it in the dmaxdar register in the dma channel. 4. fetch the source address from the descripto r and place it in the dmaxsar register in the dma channel. 5. fetch the txln length from the descriptor and place it in the dmaxtxln register in the dma channel. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 280 6. after the reads have been completed, the dma starts looking for requests and transfer data until the transfer length reaches zero or the dma receives a request eof signal. 7. when the dma receives the request eof si gnal, it does the following based upon the loop and eof bit: ? 00: the dma writes the descript or control/status word with the dmaxen bit reset to zero. ? 01: the dma requests status from the pe ripheral. it then writes the descriptor control/status word with the dmaxen bit reset to zero and the status returned from the peripheral. the dma then writes the txln length to the descriptor. ? 1x: the dma does not modify the descriptor. 8. if the halt bit is set the dma closes the current buffer but does not fetch the next descriptor. 9. once a new dmaxlar address has been up dated, the dma goes back to step 2 above and fetches the control/status byte. dma priority the dma priority is based upon the last ch annel serviced. once a channel is serviced it becomes the lowest priority channel. table 142 lists the dma priority. each dma has equal prior ity under this scheme. table 142. dma priority last channel serv iced dma priority dma0 dma1 (highest) dma2 dma3 dma0 (lowest) dma1 dma2 (highest) dma3 dma0 dma1 (lowest) dma2 dma3 (highest) dma0 dma1 dma2 (lowest) dma3 dma 0 (highest) dma 1 dma 2 dma 3 (lowest) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 281 dma bandwidth selection in the cpuctl register, the dmabw mode bits set the maximum bus bandwidth the dma is allowed. there are four mod es (for more details, refer to the zneo cpu user manual (um0188) ). table 143 lists the dma bandwidth selection. dma interrupts each dma has its own interrupt vector. for ad ditional information on the interrupts, see the interrupt section. interrupts occur on th e following conditions: ? whenever a buffer is completed which has its ieob set. ? when the upper eight bits of the transfer le ngth equal zero and the lower eight bits of the transfer length is equal to the dmaxla r[23:16] and the dma is in direct mode. ? if a buffer has been terminated by a request eof. dma request select register chanstate?channel state 0000 = dma off 0001 = direct mode, waiting for end of frame signal table 143. dma bandwidth selection bits description 00 dma uses 100% of the bandwidth 01 dma is allowed one transfer for each cpu operation 10 dma is allowed one transfer for every two cpu operations 11 dma is allowed one transfer for every three cpu operations table 144. dma select register (damxreqsel) bits 7 6 5 4 3 2 1 0 field chanstate reqsel reset 00000000 r/w rrrrr/wr/wr/wr/w addr ffe400h, ffe401h, ffe402h, ffe403h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 282 0010 = linked list mode, waiting for end of frame signal 0011 = reserved 0100 = direct mode, first byte transfer, send command 0101 = linked list mode, first byte transfer, send command 0110 = direct mode, transfer of buffer in progress 0111 = linked list mode, transfer of buffer in progress 1000 = direct mode, close descriptor 1001 = linked list mode, new list 1010 = linked list mode, close descriptor 1011-1111 = reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 283 table 145. dma request selection by channel dma0 reqsel?dma 0 request select 0000 = continuous (that is memory to memory) 0001 = timer 0 0010 = timer 1 0011 = timer 2 0100 = uart0 rxd 0101 = uart0 txd 0110 = uart1 rxd 0111 = uart1 txd 1000 = i2c rx 1001 = i2c tx 1010 = spi rx 1011 = spi tx 1100 = adc0 1101 = reserved 1110 = reserved 1111 = dma0req pin dma1 reqsel?dma 1 request select 0000 = continuous (that is memory to memory) 0001 = timer 0 0010 = timer 1 0011 = timer 2 0100 = uart0 rxd 0101 = uart0 txd 0110 = uart1 rxd 0111 = uart1 txd 1000 = i2c rx 1001 = i2c tx 1010 = spi rx 1011 = spi tx 1100 = adc0 1101 = reserved 1110 = reserved 1111 = dma1req pin www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 284 dma2 reqsel?dma 2 request select 0000 = continuous (that is memory to memory) 0001 = timer 0 0010 = timer 1 0011 = timer 2 0100 = uart0 rxd 0101 = uart0 txd 0110 = uart1 rxd 0111 = uart1 txd 1000 = i2c rx 1001 = i2c tx 1010 = spi rx 1011 = spi tx 1100 = adc0 1101 = reserved 1110 = reserved 1111 = dma2req pin dma3 reqsel?dma 3 request select 0000 = continuous (that is memory to memory) 0001 = timer 0 0010 = timer 1 0011 = timer 2 0100 = uart0 rxd 0101 = uart0 txd 0110 = uart1 rxd 0111 = uart1 txd 1000 = i2c rx 1001 = i2c tx 1010 = spi rx 1011 = spi tx 1100 = adc0 1101 = reserved 1110 = reserved 1111 = reserved table 145. dma request selection by channel (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 285 dma control registers the following section describes the dma control registers. dma control register the dma control register enables and control the dma transfer (see table 146 ). dmaxen?dma x enable . if this bit is written directly then normal mode is executed. if this bit is read in from a descrip tor then linked list mode is executed. 0 = dma is disabled. 1 = dma is enabled. loop?loop mode 0 = descriptor is modified when the buffer is closed. 1 = descriptor is not modified when buffer is closed. txsize?transfer size 00 = byte 01 = word 10 = quad 11 = reserved dstctl?destination control register 00 = destination ad dress does not change 01 = destination address increments table 146. dma control register a (dmaxctl) bits 15 14 13 12 11 10 9 8 field dmaxen loop txsize dstctl srcctl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe410h, ffe420h, ffe430h, ffe440h bits 7 6 5 4 3 2 1 0 field ieob txfr eof halt cmdstat reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ffe411h, ffe421h, ffe431h, ffe441h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 286 10 = destination address decrements 11 = reserved srcctl?source control register 00 = source address does not change 01 = source address increments 10 = source address decrements 11 = reserved ieob?interrupt on end of buffer 0 = do not generate an interrupt when the dma comp letes this buffer 1 = generate interrupt at the end of this buffer txfr?transfer to new list address . this bit is used on ly in linked list mode. 0 = increment dmaxlar by 16 at the end of this buffer. 1 = load the dmaxlar with the new list address value from the descriptor. eof?end of frame 0 = this is not a end of frame buffer 1 = this buffer is the end of the current frame halt?halt after this buffer . this bit is used on ly in linked list mode. 0 = next descriptor is loaded. 1 = the dma will halt at the end of this buffer. cmdstat?command status field on the first transfer of a buffer this fiel d is placed on the cmdbus and the cmdvalid is asserted. if the eof bit is set, the dma requests a status from the peripheral and places it in this field. in linked list mode this field get written back to the descriptor. the dma does not use this fiel d it simply passes it on. the definitions of these bits are specified in each peripheral. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 287 dma x transfer length register these two registers form a 16-bit transfer leng th. this register is decremented each time a dma transfer occurs. dma destination address these three register form the destination addr ess. this address points to where the data from the transfer will be stored. table 147. dma x transfer length high register (dmaxtxlnh) bits 7 6 5 4 3 2 1 0 field dmaxtxlnh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe412h, ffe422h, ffe432h, ffe442h table 148. dma x transfer length low register (dmaxtxlnl) bits 7 6 5 4 3 2 1 0 field dmaxtxlnl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe413h, ffe423h, ffe433h, ffe443h table 149. dma x destination address register upper (dmaxdaru) bits 7 6 5 4 3 2 1 0 field dmaxdaru reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe415h, ffe425h,ffe435h,ffe445 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 288 dma source addr ess registers the source address registers form a 24-bit sour ce address. this address is used to point to the source data for the transfer. table 150. dma x destination address register high (dmaxdarh) bits 7 6 5 4 3 2 1 0 field dmaxdarh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe416h, ffe426h, ffe436h, ffe446h table 151. dma x destination address register low (dmaxdarl) bits 7 6 5 4 3 2 1 0 field dmaxdarl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe417h, ffe427h, ffe437h, ffe447h table 152. dma x source address register upper dmaxsaru bits 7 6 5 4 3 2 1 0 field dmaxsaru reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe419h, ffe429h, ffe439h, ffe449h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 289 dma list address register this registers is written when the list mode for the dma is used . this register contains the address of the current list the dma is op erating on. writing the dmaxlarl register enables the dma for list operation. in direct mode this register is used to set a watermark interrupt. this interrupt occurs when the dmatxln[15:8] equals 0 and dmaxtx ln[7:0] equals dmaxlaru. note when using the watermark the dmaxlarl must not be written. table 153. dma x source address register high (dmaxsarh) bits 7 6 5 4 3 2 1 0 field dmaxsarh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe41ah, ffe42ah, ffe43ah, ffe44ah table 154. dma x source address register low (dmaxsarl) bits 7 6 5 4 3 2 1 0 field dmaxsarl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe41bh, ffe42bh, ffe43bh, ffe44bh table 155. dma x list address register upper dmaxlaru bits 7 6 5 4 3 2 1 0 field dmaxlaru reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe41dh, ffe42dh, ffe43dh, ffe44dh www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 290 writing the dmaxlarl register causes the dma to enter linked list mode. external dma signals two external pins are associated with each dma channel capable of external transfers (channel 3 does not have external dma ca pability). they are active low dmaxreq and dmaxack signals. dmaxack signals ar e outputs and dmaxreq are inputs. dmaxreq must be asserted for a minimum of one system clock period to generate one dma transfer. dmaxreq is le ft asserted for multiple tran sactions and deasserted once dmaxack asserts for the last appropriate transfer. table 156. dma x list address register high (dmaxlarh) bits 7 6 5 4 3 2 1 0 field dmaxlarh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe41eh, ffe42eh, ffe43eh, ffe44eh table 157. dma x list address register low (dmaxlarl) bits 7 6 5 4 3 2 1 0 field dmaxlarl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffe41fh, ffe42fh, ffe43fh, ffe44fh www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 291 dma timing external dma transfer figure 59. external dma transfer addr[23:0] data[15:0] cs rd wait (from pin) dmaack bhen / blen wr normal read cycle normal write cycle www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y dma controller zneo ? Z16F series product specification 292 external isa dma transfer figure 60. external isa dma transfer addr[23:0] data[15:0] cs rd wait (from pin) dmaack bhen / blen wr isa read cycle isa write cycle www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y option bits zneo ? Z16F series product specification 293 option bits option bits allow user configuratio n of certain aspects of the zneo ? Z16F series operation. the feature configuration data is st ored in the program me mory and read during reset. the features available for control using the option bits are: ? wdt time-out response selection?interrupt or reset. ? wdt enabled at reset. ? the ability to prevent unwanted read acc ess to user code in program memory. ? the ability to prevent accident al programming and erasure of the user code in program memory. ? voltage brownout (vbo) configuration?always enabled or disabled during stop mode to reduce stop mode power consumption. ? oscillator mode selection for high, medium , and low power crystal oscillators, or external rc oscillator. ? pwm pin set up for moto r control application. operation option bit configuration by reset each time the option bits are programmed or erased, the device must be reset for the change to take place. during any reset operation (system reset, short reset, or stop mode recovery), the option bits are automa tically read from the program memory and written to option configuration registers. th e option configuration registers control operation of the device. option bit control re gister are loaded before the device exits reset and the zneo cpu begins code execut ion. the option configuration registers are not part of the register file and are not accessible for read or write access. option bit address space the first four bytes of program memory at addresses 0000h (see table 158 on page 294) through 0003h (see table 159 on page 295) are reserved for the user option bits. these bytes are used to configure user specific op tions. you can change the option bits to meet the application needs. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y option bits zneo ? Z16F series product specification 294 program memory address 0000h option bits in this space are altered to change the chip configuration at reset. osc_sel[1:0]?oscillator mode selection 00 = on-chip oscillator configured for use with external rc networks (<4 mhz). 01 = minimum power for use with very low frequency crystals (32 khz to 1.0 mhz). 10 = medium power for use with medium fre quency crystals or ceramic resonators (0.5 mhz to 10.0 mhz). 11 = maximum power for use with high frequen cy crystals (8.0 mhz to 20.0 mhz). this setting is the default for un programmed (erased) flash. wdt_res?wdt reset 0 = wdt time-out generates an interrupt reques t. interrupts must be globally enabled for the zneo cpu to acknowled ge the interrupt request. 1 = wdt time-out causes a short reset. this setting is the default for unprogrammed (erased) flash. wdt_ao?wdt always on 0 = wdt is automatically enabled after reset. the wdt oscillator is disabled by clearing the wdten bit in the oscctl register. 1 = wdt is enabled upon execution of the wdt instruction. the wdt oscillator is disabled by clearing the wdten bit in the oscctl register. vbo_ao?voltage brownout protection always on 0 = voltage brownout protection is disabled in stop mode to reduce total power consumption. 1 = voltage brownout protection is always enabled, including during stop mode. this setting is the default for un programmed (erased) flash. dbguart?debug uart enable 0 = the debug uart option is enabled. 1 = the debug uart option is disabled. table 158. option bits at program memory address 0000h bits 7 6 5 4 3 2 1 0 field osc_sel[1:0] wdt_res wdt_ao vbo_ao dbguart fwp rp reset uuuuu u uu r/w r/w r/w r/w r/w r/w r/w r/w r/w addr program memory 0000h note: u = unchanged by reset. r/w = read/write. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y option bits zneo ? Z16F series product specification 295 fwp?flash write protect rp?read protect 0 = user program code is inaccessible. limite d control features are available through the ocd. 1 = user program code is accessible. all ocd commands are enabled. this setting is the default for unprogram med (erased) flash. program memory address 0001h option bits in this space are altered to change the chip configuration at reset. reserved these option bits are reserved for future use and must always be 1. this setting is the default for unprogram med (erased) flash. mcen?motor control enable 0 = motor control pins are enabled on reset 1 = normal pin operation pwmhi? high side off initial value 0 = the high side off value is equal to zero. 1 = the high side off value is equal to one. pwmlo ?low side off initial value 0 = the low side off value is equal to zero. 1 = the low side off value is equal to one. fwp description 0 programming, page erase, and mass erase through user code is disabled. flash operations are allowed through the on-chip debugger 1 programming, page erase, and mass erase are enabled for all of flash program memory. table 159. options bits at program memory address 0001h bits 7 6 5 4 3 2 1 0 field reserved mcen pwmhi pwmlo reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr program memory 0001h note: u = unchanged by reset. r/w = read/write. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y option bits zneo ? Z16F series product specification 296 program memory address 0002h option bits in this space are altered to change the chip configuration at reset reserved these option bits are reserved for future use an d must always be 1. this setting is the default for unprogram med (erased) flash. program memory address 0003h option bits in this space are altered to change the chip conf iguration at reset. romless 16?romless 16 select 0 = if the device is romless, the data bus is 8 bits wide and is on port e[7:0]. 1 = if the device is romless, the data bus is 16 bits wide and is on {port j[7:0], port e[7:0]} lpopt?low power option 0 = the part will come up in low power mode. the clock is divide by 8 and the flash will only be accessed the last half of the last cycle of the divide. this reduces flash power consumption. 1 = the part will come up normally. table 160. options bits at program memory address 0002h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr program memory 0002h note: u = unchanged by reset. r/w = read/write. table 161. options bits at program memory address 0003h bits 7 6 5 4 3 2 1 0 field romless 16 lpopt reserved reset uuuuuuuu r/w r/w r/w r/w r/w r/w r/w r/w r/w addr program memory 0003h note: u = unchanged by reset. r/w = read/write. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y option bits zneo ? Z16F series product specification 297 reserved these option bits are reserved for future use an d must always be 1. this setting is the default for unprogram med (erased) flash. information area data in the information area of memory cannot be altered dire ctly. if you wish to alter the factory settings, it must be done by writing to the register address identified. the part defaults to the factory settings after reset and the registers mu st be re-written to have the user settings in effect. read the informat ion area address to determine the factory settings. ipo trim registers (information area address 0 021h and 0022h) table 162 and table 163 define the ipo trim settings. they are altered after reset by accessing the ipotrim1 and ipotrim2 registers. the ipo trim table is tbd. table 162. ipo trim 1 (ipotrim1) bits 7 6 5 4 3 2 1 0 field ipo temp trim ipo trim reset llllllll r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffff_ff25h note: l = loaded at reset. r/w = read/write. this regist er is loaded from information area on reset. table 163. ipo trim 2 (ipotrim2) bits 7 6 5 4 3 2 1 0 field ipo trim reset llllllll r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffff_ff26 note: l = loaded at reset. r/w = read/write. this regist er is loaded from information area on reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y option bits zneo ? Z16F series product specification 298 adc reference voltage trim (i nformation area address 0023h) table 164 defines the adc reference voltage trim settings. they are altered after reset by accessing the adctrim register. reserved ?these bits are reserved and must be programmed to 1. adcref[4:0]?adc reference trim these bits are used to trim the adc reference voltage generator. if the part is not going to be trimmed, the value of th is register must be f0h. table 164. adc reference voltage trim (adctrim) bits 7 6 5 4 3 2 1 0 field reserved adc reference trim reset llllllll r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffff_ff27 note : l = loaded at reset. r/w = read /write. this register is loaded from information area on reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 299 on-chip debugger the zneo ? Z16F series products have an inte grated on-chip debugger (ocd) that provides the following features: ? reading and writing memory. ? reading and writing cpu registers. ? execution of cpu instructions. ? in-circuit programming and erasing of the flash. ? unlimited number of software breakpoints. ? four hardware breakpoints. ? instruction execution trace. ? single-pin serial communication interface. architecture the ocd consists of two main blocks: the transmitter/receiver unit and the debug control logic. figure 61 displays the architecture of the ocd. figure 61. on-chip debugger block diagram shifter baud rate detector & generator transmit & receive controller dbg pin cpu debug controller tx data rx data memory bus www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 300 operation for effective operation of the device, all power pins (v dd and av dd ) must be supplied with power, and all ground pins (v ss and av ss ) must be prop - erly grounded. the dbg pin must be connected to v dd through an exter - nal pull-up resistor to ensure proper operation. on-chip debug enable the dbg pin is mainly used for debugging. the ocd is always enabled by default following reset. disable the ocd after startu p and use the dbg pin as a uart or a gpio pin if the dbguart option bit has been cleared. to use the dbg pin as a uart or gpio pin, the ocd must be disabled. the ocd is disabled by clearing th e ocden bit in the debug control register (dbgctl) . the ocd cannot be disabled, if the ocdlock bit in the dbgctl register is set. serial interface the dbg pin is used for serial communicatio n. this one-pin interface is a bidirectional half-duplex open-drain interfa ce that transmits and receives data. transmit and receive operations cannot occur simultaneously. the se rial data is sent and received using the asynchronous protocol defined in rs-232. the serial pin is connected to the serial port of the pc using minimal external hardware. two different methods for connecting the serial pin to an rs-232 interface are depicted in figure 62 and figure 63 . the serial pin is open-drain and must be connected to v dd through an external pull-up resistor to ensure proper operation. figure 62. interfacing the serial pin with an rs-232 interface (1) caution: rs-232 tranceiver rs232 tx rs232 rx vdd diode 10 k dbg pin www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 301 figure 63. interfacing the serial pin with an rs-232 interface (2) serial data format the data format of the serial interface uses the asynchronous protocol defined in rs-232. each character is transmitted as 1 start bit, 8-9 data bits (least-sign ificant bit first), and 1 stop bit (see figure 64 ). figure 64. ocd serial data format each bit time is of same length. the bit pe riod is set by the baud rate generator. when the transmitter sends a character, it firs t sends a low start bit. the transmitter then waits one bit time. after the st art bit is sent, the transmitter sends the next data bit. the transmitter sends each data bit in turn, waiting one full bit time before sending the next data bit. after the last data bit is sent, the transmitter sends a high stop bit for one bit time. the receiver looks for the falling edge of the start bit. once the receiver sees the start bit is low, it waits one half bit tim e and samples the middle of the start bit. if the middle of the start bit is high, the receiver considers th is as a false start bit. the receiver ignores a false start bit and search es for another falling edge. if the mi ddle of the start bit is low, the receiver considers the start bit valid. the re ceiver will wait a full bit time from the middle of the start bit to sample the next data bit. the next data bit is sampled in the middle of the bit period. the receiver repeats this operation for each data bit, waiting one full bit time to between sampling each data bit. after the receiver has sampled the last data bit, it waits one full bit time and sample the middle of the stop bit. if the stop bit is low, the receiver detects a framing error. rs-232 tranceiver rs232 tx rs232 rx vdd open-drain 10 k dbg pin buffer st d0 d1 d2 d3 d4 d5 d6 d7 sp st = start bit sp = stop bit d0-d7 = data bits www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 302 if the stop bit is high, the data was correctly framed between a start and stop bit. after the receiver samples the middle of the stop bit, it begins searching for another start bit. the receiver does not wait for the full stop bit to be received before searching for the next start bit. this is to correct for any bit skew due to error between the tr ansmit and receive baud rate clocks. baud rate generator the baud rate generator (brg) is used to generate a bit clock for transmit and receive operations. the brg reload register is au tomatically configured by the auto-baud detector, or it is written by software. the value in the brg reload register is calculated as: this reload value is the number of system cl ocks used to transmit and receive eight data bits. the brg has a 16-bit reload counter and is clocked by the system clock. when the ocd is enabled, this register is limited to 12 bits. the minimum ba ud rate is calculated using the following equation: the minimum baud rate when the ocd is enabled is the system clock frequency divided by 512. the minimum baud rate is the system clock frequency divided by 8192 when the ocd is disabled. for asynchronous operation, the maximum baud rate is roughly the system clock frequency divided by eight (eight clocks per bi t). with slow baud rates and clean signals, you will be able to achieve asynchronous baud rates up to 4 clocks per bit. if data is synchronized with the system clock, the maxi mum baud rate is the system clock frequency (one bit per clock). the maximum baud rates are limited by the rise and fall times due to the cable impedance. table 165 lists minimum and maximum baud rates for sample crystal frequencies. table 165. ocd baud rate limits system clock frequency maximum baud rate minimum baud rate (ocden=0) minimum baud rate (ocden=1) 20.0 mhz 2.5 m baud * 2442 baud 39,062 baud 1.0 mhz 125 k baud 123 baud 1953 baud baud reload value = system clock baud rate x 8 baud reload value = system clock baud rate x 8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 303 auto-baud detector to operate using various clock frequencies over a range of baud rates, the serial interface has an auto-baud detector. the auto-baud detect or is used to automa tically setup the baud rate generator. the auto-baud detector is setup to measure one of two different auto-baud characters, 80h (default) or 0dh . the default auto-baud character 80h is compatible with previous z8 encore! ? debug interfaces. when the ocd is di sabled and the dbg pin is being used as a uart, you can switch to an auto-baud character of 0dh . the 0dh character is the ascii carriage return character and is sent using a terminal interface. when using the auto-baud character 80h , the auto-baud detector measures the period from the falling edge at the beginnin g of the start bit to the rising edge at the beginning of data bit 7. for the auto-baud character 0dh , the auto-baud detector measures the period from the rising edge at the end of the start bit to the rising edge at the beginning of the stop bit. this measured value is automatically writte n to the brg reload register once the auto-baud character is received. once config ured, the brg will generate a bit clock based on this measured character time. line control when operating at high speeds, it is appropriat e to speed up the rise and fall times of the single wire bus. three control bits are used to control the bus rise and fall times, the high drive strength enable bit, the drive high enab le bit, and the output enable control bit. the high drive strength enable bit puts the pi n into high drive mode . for information on high drive strength, see electrical characteristics on page 337. if the output enable control bit is set, the line is driven high and lo w during transmission. if the drive high control bit is set, it drives the line high for short periods when transmit- ting a logic one. this rapidly charges the inherent capacitance of the single wire bus. if both the output enable and drive high control bits are set, the line is driven high for one clock cycle when transmitting a one. if the output enable bit is clear and the drive high bit is set, the line is driven high until the input is detected high or the center of the bit time occurs, whichever is first. 32.768 khz 4096 baud 4.0 baud 64 baud * the maximum baud rate is limited by the rise and fall times due to the cable impedance. table 165. ocd baud rate limits (continued) system clock frequency maximum baud rate minimum baud rate (ocden=0) minimum baud rate (ocden=1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 304 figure 65. output driver when drive high and open drain enabled 9-bit mode the serial interface is configured to transmit and receive a ninth data bit. this ninth bit is used to transmit or receive a software generated parity bit. it is used as an address/data bit in a multi-node syst em such as rs-485. figure 66. 9-bit mode start bit flow control if flow control is needed, start bit flow contro l is used. start bit flow control requires the receiving device send the start bit. the transmit ter waits for the start bit, then transmit its data following the start bit. system clock drive high high impedance drive low { output driver logic 0 logic 1 bus voltage st d0 d1 d2 d3 d4 d5 d6 d7 sp nb st = start bit sp = stop bit nb = ninth bit d0-d7 = data bits www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 305 figure 67. start bit flow control if the standard serial port of a pc is used, transmit flow control is enabled on the zneo Z16F series device. the pc sends the start bit when receiving data by transmitting the character ffh . since character ffh is also received from a non-responsive device, space parity (parity bit always zero) must be enabled and used as an acknowledge bit. initialization the ocd ignores any data received until it receives the read revision command 00h . after the read revision comm and is received, the remainin g debug commands are issued. the packet crc is not sent for the first read revision command issued during initialization. initialization during reset the ocd is initialized during r eset. this is done by assertin g the reset pin, sending the auto-baud character, and then issuing the read revision command. when the ocd is initialized during reset, the dbghalt bit in the ocdctl register is automatically set. receiving device transmitting device single wire bus st d0 d1 d2 d3 d4 d5 d6 d7 sp st d0 d1 d2 d3 d4 d5 d6 d7 st = start bit sp = stop bit d0-d7 = data bits sp www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 306 figure 68. initialization during reset debug lock the interface has a locking me chanism to prevent user code from disabling the ocd and using the dbg pin as a uart or gpio pin. the dbglock bit in the dbgctl register prevents you from disabling the ocd and modifying any register that would inhibit communication with the ocd. the default state of the dbglock bit is set accordingly to the dbguart option bit. in order to use the dbg pin as a uart or gpio pin, you must program the dbguart option bit to zero so the ocdlock control bit is cleared after reset. after the control register is unlocked, software then clears the ocden control bit to use the dbg pin as a uart or gpio pin. if the dbguart option bit is cleared and the ocdlock control bit is not set, the ocd is still locked before code has the ch ance to disable the ocd. this is done by initializing the debugger during reset and writing the ocdlock control bit to 1. error reset the serial interface has an auto-reset mechanis m that resets the serial interface when a transmit collision or receive framing error is detected. when a transmit collision or receive framing error is detected when ocden is set, the ocd aborts any command currently in progress, transmits a serial brea k condition for 4096 system clocks, and sets the absrch bit in the dbgctl register. this break is sent to ensure the host also detects the error. a clock change invalidates th e baud reload value. commun ication cannot continue until a new autobaud reload value is set. as a resu lt, the device automatically sends a serial break to reset the communication link wh enever a clock change occurs. reset pin internal system reset debug reset 80h 00h debug pin reset timeout reset pin remains asserted idh idl www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 307 debug halt mode during debugging, it is appropriate to stop the cpu from executing instructions. this is done by placing the device in debug halt mode. the operating characteristics of the zneo Z16F series devices in debug halt mode are: ? the zneo cpu fetch unit stops, idling the zneo cpu. ? all enabled on-chip peripherals operate unless in stop mode. ? constantly refreshes the wdt, if enabled. entering debug halt mode the device enters debug halt mode by any of the following operations: ? write the dbghalt bit in the dbgctl re gister to 1 using the ocd interface. ? zneo cpu execution of brk instruction (when enabled). ? hardware breakpoint match. exiting debug halt mode the device exits debug halt mode by any of the following operations: ? clearing the dbghalt bit in the dbgctl register to 0. ? power-on reset. ? voltage brownout reset. ? asserting the reset pin low to initiate a reset. reading and writing memory most debugging functions are accomplished by reading and writing control registers. the ocd hardware has the capa bility of reading and writin g memory when the cpu is running. when a read or write request from the ocd ha rdware occurs, the ocd steals the bus for the number of cycles needed to complete the read or write operation. this bus stealing occurs on a per byte basis, not a per comman d basis. since the debugger operates serially, it takes several clock cycles to transmit or receive a character. if the debugger receives a command to read or write a block of memory, it will not steal the bus for the entire read or write command. the debugger will only steal the bus for a short period of time for each data byte. a debug write cy cle will occur after a byte has been received during a write operation. a de bug read cycle will occur when the transmit- ter is empty during a read operation. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 308 data read from or written to the ocd occurs one byte at a time. therefore, memory read and write operations occur one byte at a time. operations th at occur on multi-byte words does not occur concurrently. reading memory crc since the zneo device has such a large memo ry space and the debug interface is serial, reading massive amounts of data during debugging is time consuming. the ocd hard- ware has the capability of calculating a cycl ic redundancy check (crc) on memory to allow memory caching mechanisms to be used by the host debugging software. this crc verifies that the contents of a memory cache has not changed. when the read crc command is issued, the oc d hardware steals the cpu bus during the entire read operation. the lengt h of time it takes to genera te the crc is equal to the amount of time it takes to read the memory used in the crc calculation. the ocd hardware also has the capability of returning separate crcs for each 4k block of memory. this is used by software to determine the por tions of memory, which have been modified when the cache for a la rge block of memory is invalidated. breakpoints software breakpoints breakpoints are generated when the cpu executes the brk instruction and breakpoints are enabled. if breakpoints are not enabled, the brk instruction will vector to the system exception vector and set the ille gal instruction status bit. if a breakpoint is generated, the ocd is co nfigured to automati cally enter debug halt mode or to just loop on the in struction. if the ocd is configured to loop on the instruction, the cpu is still able to service dma and interrupt requests in the background. software polls the dbgbrk bit of the dbgctl register to determine if the ocd has reached a breakpoint. hardware breakpoint there are four hardware breakpoints on the zn eo device. when enabled, a breakpoint is generated when the program coun ter matches the value in the breakpoint register, or when a memory access occurs at the address in th e breakpoint register. a data watchpoint watches a range of addresses by selecting how many lower address bits are ignored. instruction trace trace overview the zneo has the ability to trace the instruc tion flow. if enabled, it uses existing memory to store the program counter data each time a change in execution flow occurs. this requires you to allocate memory sp ace to hold the trace information. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 309 trace events a trace event occurs anytime a call, ret, interrupt, iret, trap, jp, djnz, or excep- tion occurs. trace takes four cycles each time a trace event occurs (five cycles for irq, trap, and exceptions). trace buffer the trace buffer is controlled by two re gisters: trace control (tracectl) and trace address (traceaddr) register. the tracectl register is used to enable the trace and select the size of the trace buffer. traceaddr selects the starting address for the trace. the trace address is modulo-n based upon the size of the tr acesel field in the tracectl register. the modulo-n is zero aligned, which means that the trace buffer always wraps to zero for the selected size. for example, if the traceaddr is set to ffffb050h and the tracectl is set to 81h, the buffer is located from ffffb000h to ffffb0ffh with the first trace event to be written to ffffb050h. when the address reaches ffffb0ffh it will roll over to ffffb000h. trace buffer sizes are 128, 256, 512, 1024, 2048, 4096, 8192, and 16384 bytes. each trace event requires eight bytes giving a minimum of 16 events to a maximum of 2048 events. only the program counter values are stored. other information has to be inferred from the source code by the trace debugger. trace operation on each trace event the current program counte r is placed in memory pointed to by the traceaddr. traceaddr increments by 4 and the next state of the program counter is written to the traceaddr. traceaddr increments by 4 again. traceaddr always points to the next data to be writte n. the lower two bits of the traceaddr are always zero. extracting trace information the trace information is extr acted by reading the data fro m the selected trace memory area. the data is then interprete d by the trace debugger software. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 310 on-chip debugger commands the hardware ocd supports several co mmands for controlling the device. i n the following list of commands, data sent fro m the host to the ocd is identified by ? dbg <-- data ?. data sent from the ocd back to the host is identified by ? dbg --> data ? . multiple bytes transmitted are repres ented with double arrows ?<>?. ? read revision ? the read revision command re turns the revision identifier. dbg <-- 0000_0000 dbg --> revid[15:8] dbg --> revid[7:0] dbg --> crc[0:7] ? read status register ? the read status register command returns the contents of the ocdstat register. dbg <-- 0000_0001 dbg --> status[7:0] dbg --> crc[0:7] ? read control register ? the read control register command returns the contents of the ocdctl register . dbg <-- 0000_0010 dbg --> ocdctl[7:0] dbg --> crc[0:7] ? write control register ? the write control register command writes data to the ocdctl register. dbg <-- 0000_0011 dbg <-- ocdctl[7:0] dbg --> crc[0:7] ? read registers ? the read registers command returns the contents of cpu registers r15 through r0. dbg <-- 0000_0100 dbg ->> regdata[31:24] dbg ->> regdata[23:16] dbg ->> regdata[15:8] dbg ->> regdata[7:0] dbg --> crc[0:7] ? write registers ? the write registers command writes data to cpu registers r15 through r0. dbg <-- 0000_0101 dbg <<- regdata[31:24] dbg <<- regdata[23:16] dbg <<- regdata[15:8] dbg <<- regdata[7:0] dbg --> crc[0:7] www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 311 ? read pc ? the read program counter command re turns the contents of the program counter. dbg <-- 0000_0110 dbg --> 00h dbg --> pc[23:16] dbg --> pc[15:8] dbg --> pc[7:0] dbg --> crc[0:7] ? write pc ? the write program counter comm and writes data to the program counter. dbg <-- 0000_0111 dbg <-- 00h dbg <-- pc[23:16] dbg <-- pc[15:8] dbg <-- pc[7:0] dbg --> crc[0:7] ? read flags ? the read flags command return s the contents of the cpu flags. dbg <-- 0000_1000 dbg --> 00h dbg --> flags[7:0] dbg --> crc[0:7] ? write instruction ? the write instruction command writes one word of opcode to the cpu. dbg <-- 0000_1001 dbg <-- opcode[15:8] dbg <-- opcode[7:0] dbg --> crc[0:7] ? read register ? the read register command returns the contents of a single cpu register. dbg <-- {0100,regno[3:0]} dbg --> regdata[31:24] dbg --> regdata[23:16] dbg --> regdata[15:8] dbg --> regdata[7:0] dbg --> crc[0:7] ? write register ? the write register command writes data to a single cpu register. dbg <-- {0101,regno[3:0]} dbg <-- regdata[31:24] dbg <-- regdata[23:16] dbg <-- regdata[15:8] www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 312 dbg <-- regdata[7:0] dbg --> crc[0:7] ? read memory ? the read memory command read s data from memory. the memory address is sign extended. dbg <-- {1000,size[3:0]} dbg <-- addr[15:8] dbg <-- addr[7:0] dbg ->> 1 to 16 bytes of data dbg --> crc[0:7] ? write memory ? the write memory command writ es data to memory. the memory address is sign extended. dbg <-- {1001,size[3:0} dbg <-- addr[15:8] dbg <-- addr[7:0] dbg <<- 1 to 16 bytes of data dbg --> crc[0:7] ? read memory ? the read memory command reads data from memory . dbg <-- {1010,size[3:0} dbg <-- size[11:4] dbg <-- 00h dbg <-- addr[23:16] dbg <-- addr[15:8] dbg <-- addr[7:0] dbg ->> 1 to 4096 bytes of data dbg --> crc[0:7] ? write memory ? the write memory command writes data to memory . dbg <-- {1011,size[3:0} dbg <-- size[11:4] dbg <-- 00h dbg <-- addr[23:16] dbg <-- addr[15:8] dbg <-- addr[7:0] dbg <<- 1 to 4096 bytes of data dbg --> crc[0:7] ? read memory crc ? the read memory crc command computes and return the crc of a block of memory. dbg <-- {1110,blockcount[3:0]} dbg <-- blockcount[11:4] dbg <-- 00h dbg <-- addr[23:16] dbg <-- {addr[15:12],xxxx} dbg --> memorycrc[0:7] www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 313 dbg --> memorycrc[8:15] dbg --> crc[0:7] the memorycrc is computed on memory in increments of 4k blocks. the blockcount field determines how many blocks of memory to compute the memorycrc on. ? read each memory crc ? the read memory crc command computes and return the crc of a block each 4k memory block. dbg <-- {1111,blockcount[3:0]} dbg <-- blockcount[11:4] dbg <-- 00h dbg <-- addr[23:16] dbg <-- {addr[15:12],xxxx} dbg ->> memorycrc[0:7] dbg ->> memorycrc[8:15] dbg --> crc[0:7] the memorycrc is computed on memory in incr ements of 4k blocks. the crc is returned for each 4k block and is r eset at the start of each block. the blockcount field determines how many blocks of memory to compute the memorycrc on. the on-chip debugger commands are summarized in table 166 . table 166. on-chip debugger commands debug command command byte disabled by read protect option bit read revision 0000-0000 ? read ocd status register 0000-0001 ? read ocd control register 0000-0010 ? write ocd control register 0000-0011 cannot single step (bit0 has not effect) read registers (cpu registers r15-r0) 0000-0100 yes write registers (cpu registers r15-r0) 0000-0101 yes read program counter 0000-0110 yes write program counter 0000-0111 yes read flags 0000-1000 yes write instruction 0000-1001 yes read register (single cpu register) 0100-(regno[3:0]) yes write register (single cpu register) 0100-(regno[3:0]) yes www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 314 cyclic redundancy check to ensure transmitted and received data is free of errors, the ocd transmits an 8-bit cyclic redundancy check (crc) at the end of each command. the crc is enabled after the ocd is initialized, it is not sent with the first read revi sion command. this crc is disabled by clearing the crce n bit of the dbgctl register. the crc is reset at the beginning of each co mmand and is computed on the data received from and sent to the host. the crc is cal culated using the atm-8 hec polynomial x 8 +x 2 +x 1 +x 0 . the crc is preset to all ones. data is shifted through the polynomial lsb first. the resulting crc is reversed and inverted. the check value is cfh . memory cyclic redundancy check the read memory crc comman d computes the crc on memory in 4k blocks, up to 4k blocks at a time (16m of data). the memo ry crc is computed us ing the 16-bit ccitt polynomial x 16 +x 12 +x 5 +x 0 . the crc is preset to all ones. data is shifted through the polynomial lsb first. the resulting crc is reversed and inverted. the check value is f0b8h . uart mode when the ocd is disabled, the dbg pin is used as a single pin half-duplex uart. when the serial interface is in uart mo de, data received on the single wire bus is written to the receive data register. data wr itten to the transmit data regist er is transmitted on the sin- gle wire bus. in uart mode, the auto-baud hard ware is used to configure the brg, or the baud rate registers are written to set a specific baud rate. read memory (short -address is sign extended) 0100-(regno[3:0]) read only unprotected memory locations write memory (short -address is sign extended) 0100-(regno[3:0]) write on ly unprotected memory locations read memory (long) 1010-size[3:0] read only unprotected memory locations write memory (long) 1011-size[3:0] write only unprotected memory locations read memory crc 1110-blockcount[3:0] ? read each memory crc 1111-blockcount[3:0] ? note: unlisted command byte values are reserved. table 166. on-chip debugger commands (continued) debug command command byte disabled by read protect option bit www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 315 the uarten control bit must be set to one to use the serial interface as a uart. clearing the uarten control bit to zero will preven t data received on the dbg pin from being written to the receive data register. clea ring the uarten control bit to zero also prevents data written to the transmit data register from be ing transmitted on the single pin interface. if the uart is disabled, data is still written to the receive data register and read from the transmit data register. these actions still generates uart interrupts. the uarten con- trol bit only prevents data from being tr ansmitted to or received from the dbg pin. serial errors the serial interface detects th e following error conditions: ? receive framing error (recei ved stop bit is low). ? transmit collision (ocd releases the bus high to send a logi c 1 and detects it is low). ? receive overrun (received data before previously received data read). ? receive break detect (10 or more bits low). transmission of data is prevented if the tran smit collision, receive framing error, receive break detect, receive overrun, or receive data register full status bits are set. interrupts the debug uart generates interrupts during the following conditions: ? receive data register is full (includes rx framing error and rx overrun error). ? transmit data register is empty. ? auto-baud detector loads the brg (auto-baud character received). ? receive break detected. dbg pin used as a gpio pin the dbg pin is used as a gpio pin. the seri al interface cannot be used for debugging when the dbg pin is configured as a gpio pi n. to set up the dbg pin as a gpio pin, software must clear the dbguart option bit and ocden control bit. software uses the pin as an input by clearing the output enable control bit. the pin status bit in line control register (dbglcr) reflects the state of the dbg pin. the dbg pin is configured as an output pin by setting the output en able control bit. the logic state of the idle bit in line control register (dbglcr) is driven onto the dbg pin. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 316 control register definitions receive data register the receive data register (dbgrxd) holds data received by the serial uart. rxdata?receive data in uart mode, data received on the serial interface is tran sferred from the shift register into this register. this register is written to simulate data received if the dbg pin is being used by the ocd. transmit data register the transmit data register (dbgtxd) holds data to be tran smitted by the serial uart. txdata?transmit data in uart mode, data written to this register is transmitted on the serial interface. this reg- ister is read to simulate data transmitte d if the dbg pin is being used by the ocd. table 167. receive data register (dbgrxd) bits 7 6 5 4 3 2 1 0 field rxdata reset xx r/w r/w addr ff_e080 table 168. transmit data register (dbgtxd) bits 7 6 5 4 3 2 1 0 field txdata reset xx r/w r/w addr ff_e081 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 317 baud rate reload register the baud rate reload register (dbgbr) is used to configure th e baud rate of the serial communication stream. this regi ster is automatically set by the auto-baud detector. this register cannot be written by the cpu when ocdlock is set. reload ?this value is the baud rate reload valu e used to generate a bit clock. it is calculated as line control register the line control register (dbglcr) controls the state of the uart. this register cannot be written by the cpu when ocdlock is set. oe?output enable this bit controls the output driver. if the uart is enabled, this bit controls the output driver during transmission only. 0 = pin is open-drain during uart transmit. pi n behaves as an input if uart is disabled. 1 = pin is driven during transmission if uart is enabled. pin is an output if uart is disabled. table 169. baud rate reload register (dbgbr) bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field reload reset 0000h r/w r/w addr ff_e082-ff_e083 table 170. line control register (dbglcr) bits 7 6 5 4 3 2 1 0 field oe tdh hds txfc nben nb out pin reset 0000001x r/w r/wr/wr/wr/wr/wr/wr/w r addr ff_e084 reload = system clock baud rate x 8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 318 tdh?transmit drive high this control bit causes the interface to drive the line high when a lo gic 1 is being transmit- ted. if oe is zero, the line stops being driven wh en the input is high or at the center of the bit, whichever is first. if oe is one, the line is driven high for one clock cycle. this bit is ignored if debug mode is zero and the uart is disabled. 0 = transmit drive high disabled. 1 = transmit drive high enabled. hds?high drive strength this control bit enabled high driv e strength for the output driver. 0 = low drive strength 1 = high drive strength txfc?transmitter start bit flow control this control bit enables start bit flow control on the transm itter. the transmitter waits until a remote device sends a start b it before transmitting its data. 0 = transmitter start bit flow control disabled. 1 = transmitter start bit flow control enabled. nben?9-bit mode enable this control bit enables transmission and reception of a ninth data bit. 0 = nine bit mode disabled. 1 = nine bit mode enabled. nb?value of ninth bit this bit is the value of the ninth data bit. when written, this reflects the ninth data bit that will be transmitted if nine bit mode is enabled. when read, this bit reflects the value of the ninth bit of the last nine bit character received. 0 = ninth bit is zero. 1 = ninth bit is one. out?output state this control bit sets the state of the output transceiver. if the uart is enabled, this bit must be set to one to idle high. clearing th is bit to zero when the uart is enabled will transmit a break condition. if the uart is disabl ed, this logic value w ill be driven onto the pin if oe is set. this bit is ignored in debug mode. 0 = transmit break if uart enabled. drive low if uart disabled and output enabled. 1 = idle high if uart enabled. drive high if uart disabled and output enabled. pin?debug pin this bit reflects the state of the dbg pin. 0 = dbg pin is low. 1 = dbg pin is high. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 319 status register the status register (dbgstat) contains status information about the state of the uart. rdrf?receive data register full this bit reflects the status of the receive data register. when data is written to the receive data register, or data is transferred from the sh ift register to the receive data register, this bit is set to one. when the receive data register is read, this bit is cl eared to zero. this bit is also cleared to zero by writing a one to this bit. 0 = receive data register is empty. 1 = receive data register is full. rxov?receive overrun this bit is set when a receive overrun occurs. a receive overrun occurs when there is data in the receive data register and an other byte is written to this register. 0 = receive overrun has not occurred 1 = receive overrun has occurred. rxfe?receive framing error this bit is set when a receiv e framing error has been detected. this bit is cleared by writing a one to this bit. 0 = no framing error detected. 1 = receive framing error detected. rxbrk?receive break detect this bit is set when a break condition has been detected. this occurs wh en 10 or more bits received are low. this bit is cl eared by writing a one to this bit. 0 = no break detected. 1 = break detected. tdre?transmit data register empty this bit reflects the status of the transmit data register. when the transmit data register is written, this bit is cleared to zero. when data from the tran smit data register is read or transferred to the transmit shift re gister, this bit is set to one. this bit is written to one to abort the transmission of data being held in the transmit data register. 0 = transmit data register is full. 1 = transmit data register is empty. table 171. status register (dbgstat) bits 7 6 5 4 3 2 1 0 field rdrf rxov rxfe rxbrk tdre txcol rxbusy txbusy reset 00001000 r/w r/w1c r/w1c r/w1c r/w1c r/w1s r/w1c r r addr ff_e085 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 320 txcol?transmit collision this bit is set when a transmit collision occurs. this bit is cleared by writing a one to this bit. 0 = no collision has been detected. 1 = transmit collision has been detected. rxbusy?receiver busy this bit is set when the receive r is receiving the data. multi-ma ster systems uses this bit to ensure the line is idle before sending the data. 0 = receiver is idle. 1 = receiver is receiving data. txbusy?transmitter busy this bit is set when th e transmitter is sending the data. this bit is used to determine when to turn off a transceiver for rs-485 applications. 0 = transmitter is idle. 1 = transmitter is sending the data. control register the control register (dbgctl) sets the mode of the serial interface. ocdlock?on-chip debug lock this bit locks the debug control register so it cannot be written by the cpu. this bit is automatically set if the dbguart option bit is in its default erased state (one). 0 = debug control register unlocked. 1 = debug control register locked. ocden?on-chip debug enable this bit is set when the ocd is enabled. when this bit is set, received data is interpreted as debug command. to use the dbg pin as a uart or gpio pin, this bit must be cleared to zero by software. this bit cannot be written by the cpu if ocdlock is set. 0 = ocd is disabled. 1 = ocd is enabled. table 172. control register (dbgctl) bit 7 6 5 4 3 2 1 0 field ocdlock ocden reserved crcen uarten abchar absrch reset 1 1 00 1001 r/w r/w r/w r r/w r/w r/w r/w addr ff_e086 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 321 reserved these bits are reserved. crcen?crc enable if this bit is set, a crc is appended to the en d of each debug comman d. clearing this bit will disable transmission of the crc. 0 = crc disabled 1 = crc enabled uarten?uart enable this bit is used to enable or disabl e the uart. this bit is ignored when ocden is set. 0 = uart disabled. 1 = uart enabled. abchar?auto-baud character this bit selects the character used during au to-baud detection. this bit cannot be written by the cpu if ocden is set. 0 = auto-baud character to be measured is 80h . 1 = auto-baud character to be measured is 0dh . absrch?auto-baud search mode this bit enables auto-baud search mode. when th is bit is set, the next character received is measured to set the baud rate reload register . this bit clears itself to zero once the reload register has been written. this bit is automatically set when ocden is set if a serial communication error occurs . this bit cannot be written by the cpu if the ocden bit is set. 0 = auto-baud search disabled. 1 = auto-baud search enabled. ocd control register the ocd control register (ocdctl) controls the state of the cpu. this register puts the cpu in debug ha lt mode, enable break points, or single step an instruction. dbghalt?debug halt setting this bit to one causes th e device to enter debug ha lt mode. when in debug halt mode, the cpu stops fetching instructions. clearing this bit causes the cpu to start running again. this bit is au tomatically set to one when a breakpoint occurs if the table 173. ocd control register (ocdctl) bits 7 6 5 4 3 2 1 0 field dbghalt brkhalt brken dbgstop reserved step reset 0000 000 0 r/w r/w r/w r/w r/w r r/w www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 322 brkhalt bit is set. 0 = the device is running. 1 = the device is in debug halt mode. brkhalt?breakpoint halt this bit determines what actio n the ocd takes when a breakpoin t occurs. if this bit is set to one, then the dbghalt bit is automatica lly set to one when a breakpoint occurs. if brkhalt is zero, then the cp u will loop on the breakpoint. 0 = cpu loops on current instruction when breakpoint occurs. 1 = a breakpoint sets dbghalt to one. brken?enable breakpoints this bit controls the behavior of the brk instruction and the hardware breakpoint. by default, these generate an illegal instruction system trap. if this bit is set to one, these events generate a breakpoint instead of a sy stem trap. the resulting action depends upon the brkhalt bit. 0 = brk instruction and hardware break point generates system trap. 1 = brk instruction and hardware break point generates a breakpoint. dbgstop?debug stop mode this bit controls the system clock behavior in stop mode. when set to one, the system clock will continue to operate in stop mode. 0 = stop mode debug disabled. system clock stops in stop mode. 1 = stop mode debug enabled. system clock runs in stop mode. reserved this bit is reserved and must be written to zero. step?single step an instruction this bit is used to single step an instruc tion when in debug halt mo de. this bit is auto- matically cleared after an instruction is executed. 0 = idle 1 = single step an instruction. ocd status register the ocd status register (ocdstat) reports status information about the current state of the system. table 174. ocd status register (ocdstat) bits 7 6 5 4 3 2 1 0 field dbghalt dbgbrk halt stop rpen reserved tdrf rdre reset 0 0000001 r/w r rrrrrrr www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 323 dbghalt?debug halt mode this status bit indicates if the cp u is stopped and in debug halt mode. 0 = device is running 1 = cpu is in debug halt mode dbgbrk?debug break this bit indicates if the cpu has reached a brk instruction. this bit is set when a brk instruction is executed. it is cleared when the dbghalt control bit is written to zero. halt?halt mode 0 = the device is not in halt mode. 1 = the device is in halt mode. stop?stop mode 0 = the device is not in stop mode. 1 = the device is in stop mode. rpen?read protect enabled 0 = memory read protect is disabled. 1 = memory read protect is enabled. tdrf?transmit data register full this bit is set when the transmit data register is full. 0 = transmit data register is empty 1 = transmit data register is full rdre?receive data register empty this bit indicates when the re ceive data register is empty. 0 = receive data register is full. 1 = receive data register is empty. reserved these bits are reserved and always read back zero. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 324 hardware breakpoint registers the hardware breakpoint register (hwbpn) is used to set hardware breakpoints. pc?break on program counter match this bit will enable th e hardware breakpoint. 0 = break on program counter match disabled. 1 = break on program counter match enabled. st?status this bit is set when a ha rdware breakpoint occurs. 0 = no breakpoint occurred since th is bit was last written to zero. 1 = breakpoint has occurred or this bit written to one. rd?break on data read this bit will enable the hardwa re watchpoint for data reads. 0 = hardware watchpoint on read disabled. 1 = hardware watchpoint on read enabled. wr?break on data write this bit will enable the hardwa re watchpoint for data writes. 0 = hardware watchpoint on data write disabled. 1 = hardware watchpoint on data write enabled. mask?watchpoint address mask the mask field specifies the number of bits in addr to ignore when comparing against addresses for read and write watchpoints. the ma sk is set to ignore 0 to 15 of the lower address bits. this allows the watchpoint to monitor a memory block up to 32k in size. table 175. hardware breakpoint register (hwbpn) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field pc st rd wr mask addr[23:16] reset 0000 0000 00h r/w r/w r/w r/w r/w r/w r/w addr ff_e090-ff_e091,ff_e094-ff_e095,ff_e098-ff_e099,ff_e09c-ff_e09d bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field addr[15:0] reset 0000h r/w r/w addr ff_e092-ff_e093,ff_e096-ff_e097, ff_e09a-ff_e09b,ff_e09e-ff_e09f www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 325 addr?breakpoint address this is the address to match when generating a breakpoint. trace control register the trace control register (tracectl) register is used to enable the trace operation. it also selects the size of the trace buffer. traceen?trace enable 0 = trace is disabled. 1 = traces is enabled reserved - these bits are reserved. tracesel?trace size select 000 ? 128 bytes (16 events) 001 ? 256 bytes (32 events) 010 ? 512 bytes (64 events) 011 ? 1024 bytes (128 events) 100 ? 2048 bytes (256 events) 101 ? 4096 bytes (512 events) 110 ? 8192 bytes (1024 events) 111 ? 16384 bytes (2048 events) table 176. trace control register (tracectl) bits 7 6 5 4 3 2 1 0 field traceen reserved tracesel reset 0 0000 000 r/w r/w r r r r r/w addr ff_e013 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip debugger zneo ? Z16F series product specification 326 trace address register the trace address (traceaddr) register points to the next data trace location. reserved ? these bits are reserved. traceaddr?trace address these bits form a 24 bit address used by the trace logic to store the next pc value to memory. table 177. trace address (traceaddr) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field reserved traceaddr[23:16] reset 00h xxh r/w rr/w addr ff_e014 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field traceaddr[15:2] 00 reset xxxxh 00 r/w r/w r addr ff_e016 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip oscillator zneo ? Z16F series product specification 327 on-chip oscillator the products in the zneo ? Z16F series feature an on-chip oscillator for use with external crystals with frequencies from 32 khz to 20 mhz. in add ition, the oscillator supports external rc networks with osc illation frequencies up to 4 mhz or ceramic resonators with oscillation frequencies up to 20 mhz. this oscillator genera tes the primary system clock for the internal zneo cpu and the majority of the on-chip peripherals. alternatively, the x in input pin also accept a cmos-level clock input signal (32 khz to 20 mhz). if an external clock genera tor is used, the x out pin must be left unconnected. when configured for use with cr ystal oscillators or external cl ock drivers, the frequency of the signal on the x in input pin determines the frequency of the system clock (that is, no internal clock divider). in rc operation, the system clock is driven by a clock divider (divide by 2) to ensure 50% duty cycle. operating modes the zneo Z16F series products support four different oscillator modes: ? on-chip oscillator configured for use with external rc networks (<4 mhz). ? minimum power for use with very low fre quency crystals (32 khz to 1.0 mhz). ? medium power for use with medium frequ ency crystals or ceramic resonators (0.5 mhz to 10.0 mhz). ? maximum power for use with high frequency crystals or ceramic resonators (8.0 mhz to 20.0 mhz). the oscillator mode is selected through user -programmable option b its. for more informa- tion, see option bits on page 293. crystal oscillator operation figure 69 on page 328 displays a recommended configuration for connection with an external fundamental mode, parallel-resonant crystal operating at 20 mhz. recommended 20 mhz crystal specifications are provided in table 178 on page 328. resistor r1 is optional and limits total power dissipation by th e crystal. the printed circuit board layout must add no more than 4 pf of stray capacitance to either the x in or x out pins. if oscillation does not occur, it reduce the values of capacitors c1 and c2 to decrease loading. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip oscillator zneo ? Z16F series product specification 328 figure 69. recommended 20 mhz crystal oscillator configuration table 178. recommended crystal oscillator specifications (20 mhz operation) parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s )25 maximum load capacitance (c l ) 20 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum c2 = 22 pf c1 = 22 pf crystal xout xin on-chip oscillator r1 = 220 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip oscillator zneo ? Z16F series product specification 329 oscillator operation with an external rc network figure 70 displays a recommende d configuration for conn ection with an external resistor-capacitor (rc) network. figure 70. connecting the on-chip oscillator to an external rc network an external resistance value of 15 k is recommended for oscillator operation with an external rc network. the minimum resistan ce value to ensure operation is 10 k . the typical oscillator frequency is estimated from the values of the resistor ( r in k ) and capacitor ( c in pf) elements usi ng the following equation: figure 71 on page 330 displays the typical (3.3 v and 25 c) oscillator frequency as a function of the capacitor ( c in pf) employed in the rc network assuming a 15 k external resistor. for very small values of c, the parasitic capacitance of the oscillator xin pin and the printed circuit board must be included in the estimation of the oscillator frequency. c x in r v dd oscillator frequency (khz) 1 6 10 1.5 rc () ----------------- --------------- = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y on-chip oscillator zneo ? Z16F series product specification 330 figure 71. typical rc oscillator frequency as a function of the external capacitance with a 15 k resistor 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 c (pf) f (khz) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y oscillator control zneo ? Z16F series product specification 331 oscillator control the zneo ? Z16F series uses three possible user-selectable clocking schemes: ? trimmable internal precision oscillator. ? on-chip oscillator using off-chip crystal/ resonator or external clock driver. ? on-chip low precision watchdog timer oscillator. in addition, zneo Z16F series contain clock failure detection and recovery circuitry, allowing continued operation despite a failure of the primary oscillator. the on-chip system clock frequency is reduced through a clock divider allowing reduced dynamic power dissipation. the flash is powered down during portions of the clock period when running slower than 10 mhz. operation this section explains the logic used to select the system clock, divide down the system clock, and handle oscillator failures. a desc ription of the specific operation of each oscillator is outlined elsewh ere in this document. see watchdog timer on page 239, internal precision oscillator on page 335, and on-chip oscillator on page 327. system clock selection the oscillator control block selects from the available clocks. table 179 on page 331 details each clock source and its usage. table 179. oscillator configuration and selection clock source characteristics required setup internal precision oscillator ? 5.5 mhz ? high precision possible when trimmed ? no external components required ? this is the reset default. external crystal/ resonator/ external clock drive ? 0 to 20 mhz ? very high accuracy (dependent on crystal/resonator or external source) ? requires external components ? configure option bits for correct external oscillator mode ? unlock and write osc illator control register (oscctl) to enable external oscillator ? wait for required stabilization time ? unlock and write osc illator control register (oscctl) to select external oscillator internal watchdog timer oscillator ? 10 khz nominal ? low accuracy ? no external components required ? low power consumption ? unlock and write osc illator control register (oscctl) to enable and select internal wdt oscillator www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y oscillator control zneo ? Z16F series product specification 332 unintentional access to the oscillator contro l register (oscctl) stops the chip by switching to a non-functioning oscillator. accidental alteration of the oscctl register is prevented by a locking/unlockin g scheme. to write the register, unlock it by making two writes to the oscctl register with the values e7h followed by 18h . a third write to the oscctl register then changes the value of the re gister and returns the register to a locked state. any other sequence of oscillator contro l register writes has no effect. the values written to unlock the register mu st be ordered correctly, but n eed not be consecutive. it is possible to access other registers with in the locking/unlocking operation. clock selection fol lowing system reset the internal precision oscillator is selecte d following a system reset. startup code after the system reset changes the system clock source by un locking and configuring the oscctl register. if the lpopt bit in program memory address 0003h is zero, flash low power mode is enabled during reset. wh en flash low power mode is enabled during reset, the flpen bit in the oscillator control register (oscctl) will be set and the div field of the oscdiv register will be set to 08h . clock failure detection and recovery primary oscillator failure the zneo Z16F series generates a system exception when a failure of the primary oscillator occurs if the pofen bit is set in the oscctl register. to maintain system function in this situation, th e clock failure recovery circ uitry automatically forces the watchdog timer oscillator to drive the system clock. although this oscillator runs at a much lower frequency than the original system clock, the cpu continues to operate, allowing execution of a clock failure vector a nd software routines th at either remedy the oscillator failure or issue a failure alert. this automatic switch-over is not available if the wdt is the primary oscillator. the primary oscillator failure detection circ uitry asserts if the system clock frequency drops below 1 khz 50%. for operating frequencies below 2 khz, do not enable the clock failure circuitry ( pofen must be deserted in the oscctl register). watchdog timer failure in the event of a watchdog timer oscillator failure, a system exception is used if the wdfen bit of the oscctl register is set. this event does not trigger an attendant clock switch-over, but alerts the cpu of the failure. after a wdt failure, it is no longer possible to detect a primary oscillator failure. the watchdog timer oscillator failure detec tion circuit counts system clocks while looking for a wdt clock. the logic counts 8 000 system clock cycles before determining that a failure occurred. the system clock rate determines the speed at which the wdt failure is detected. a very slow system cl ock results in very slow detection times. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y oscillator control zneo ? Z16F series product specification 333 if the wdt is the primary oscillator or if the watchdog timer oscillator is disabled, de-assert the wdfen bit of the oscctl register. oscillator control register definitions oscillator control register the oscillator control register (oscctl) en ables or disables the various oscillator circuits, enables/disables the failure detection/recovery circ uitry, actively powers down the flash, and selects the primary osc illator, which become s the system clock. the oscillator control register must be un locked before writing. writing the two-step sequence e7h followed by 18h to the oscillator control register address unlocks it. the register locks after completion of a register write to the oscctl. table 180. oscillator control register (oscctl) bits 7 6 5 4 3 2 1 0 field inten xtlen wdten pofen wdfen flpen scksel reset 101000* 00 r/w r/w r/w r/w r/w r/w r/w r/w addr ff_e0a0h * the reset value is 1 if the option bit lpopt is 0. bit position value (h) description [7] inten 0 internal precision oscillator enable internal precision oscillator is disabled. 1 internal precision oscillator is enabled. [6] xtlen 0 crystal oscillator enable crystal oscillator is disabled. 1 crystal oscillator is enabled. [5] wdten 0 wdt oscillator enable wdt oscillator is disabled. 1 wdt oscillator is enabled. [4] pofen 0 primary oscillator failu re detection enable failure detection and recove ry of primary oscillator is disabled. this bit is cleared automatically if a primar y oscillator failure is detected. 1 failure detection and recovery of primary oscillator is enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y oscillator control zneo ? Z16F series product specification 334 oscillator divide register the oscillator divide register (oscdiv) provid es the value to divide the system clock by. the oscillator divide register must be unlo cked before writing. writing the two-step sequence e7h followed by 18h to the oscillator control register address unlocks it. the register locks after completion of a register write to the oscdiv. [3] wdfen 0 wdt oscillator failure detection enable failure detection of wd t oscillator is disabled.this bit is cleared automatically if a wdt osc illator failure is detected. 1 failure detection of wd t oscillator is enabled. [2] flpen 0 flash low power mode enable flash low power mode is disabled. 1 flash low power mode is enabled. t he flash will be powered down during idle periods of the clock and powered up during flash reads. this bit must only be set if the frequency of the primary oscillator source is 8 mhz or lower. the reset value of this bit is controlled by the lpopt option bit during reset. [1:0] scksel 00 01 10 11 system clock oscillator select internal precision oscillator functi ons as system clock at 5.6 mhz. crystal oscillator or external clo ck driver functions as system clock. reserved. watchdog timer oscillator functions as system clock. table 181. oscillator divide register (oscdiv) bits 7 6 5 4 3 2 1 0 field div reset 00h* r/w r/w addr ff_e0a1h * the reset value is 08h if the option bit lpopt is 0. bit position value (h) description [7:0] div 00h to ffh oscillator divide 00h - divider is disabled, all other entr ies are the divide value for scaling the system clock. bit position value (h) description www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y int ernal precision oscillator zneo ? Z16F series product specification 335 internal precision oscillator the internal precision oscillator (ipo) is de signed for use without external components. nominal untrimmed accuracy is approximately 30%. you can manually trim the oscillator to achieve a 4% frequ ency accuracy over the oper ating temperature and supply voltage range of the device. the ipo features include: ? on-chip rc oscillator which does not require external components. ? nominal 30% accuracy without trim or manu ally trim the oscillato r to achieve a 4%. ? typical output frequency of 5.5296 mhz. ? trimming possible through flash option bits with user override. ? eliminates crystals or ceramic resonato rs in applications where high timing accuracy is not required. operation the internal oscillator is an rc relaxatio n oscillator and has its sensitivity to power supply variation minimized. by using ratio tracking thresholds, the effect of power supply voltage is cancelled out. the dominant source of oscillator error is the absolute variance of chip level fabricated componen ts, such as capacitors. an 8-bit trimming register, incorporated into th e design, allows compensation of absolute variation of oscillator frequency. after it is calibrated, the oscillator frequ ency is relatively stable and does not require subsequent calibration. by default, the oscillator is configured thro ugh the flash option bits. however, the user code overrides these trim values as described in option bit configuration by reset on page 293. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y int ernal precision oscillator zneo ? Z16F series product specification 336 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 337 electrical characteristics all data in this chapter is pre-qualificatio n and pre-characterization and is subject to change. absolute maximum ratings stress greater than those listed in table 182 may cause permanent damage to the device. these ratings are stress ratings only. opera tion of the device at any condition outside those indicated in the opera tional sections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods affects device reliability. for improved reliability, unused in puts must be tied to one of the supply voltages (v dd or v ss ). table 182. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias ?40 +125 c storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 +5.5 v 1 voltage on v dd pin with respect to v ss ?0.3 +3.6 v 2 maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin ?25 +25 ma 100-pin lqfp maximum ratings at ?40 c to 70 c total power dissipation 1325 mw maximum current into v dd or out of v ss 368 ma 100-pin lqfp maximum ratings at 70 c to 125 c total power dissipation 482 mw maximum current into v dd or out of v ss 134 ma 80-pin qfp maximum ratings at ?40 c to 70 c total power dissipation 550 mw maximum current into v dd or out of v ss 150 ma 80-pin qfp maximum ratings at 70 c to 125 c total power dissipation 200 mw maximum current into v dd or out of v ss 56 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 338 68-pin plcc maximum ratings at ?40 c to 70 c total power dissipation 1.0 w maximum current into v dd or out of v ss 275 ma 68-pin plcc maximum ratings at 7 0 c to 125 c total power dissipation 500 w maximum current into v dd or out of v ss 140 ma 64-pin lqfp maximum ratings at ?40 c to 70 c total power dissipation 1.0 w maximum current into v dd or out of v ss 275 ma 64-pin lqfp maximum ratings at 7 0 c to 125 c total power dissipation 540 w maximum current into v dd or out of v ss 150 ma notes 1. this voltage applies to 5 v tolerant pins which are port a, c, d, e, f, and g pins (except pins pc0 and pc1). 2. this voltage applies to vdd, avdd, pins supporting analog input (ports b and h), pins pc0 and pc1, reset, dbg, and xin pins which are non 5 v tolerant pins. table 182. absolute maximum ratings (continued) parameter minimum maximum units notes www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 339 dc characteristics table 183 lists the dc characteristics of the zneo ? Z16F series products. all voltages are referenced to v ss , the primary system ground. any pa rameter value in the typical col- umn is from characterization at 3.3 v and 0 c. these values are provided for design guid- ance only and are not tested in production. table 183. dc characteristics symbol parameter t a = ?40 c to 125 c units conditions min typ max v dd supply voltage 2.7 ? 3.6 v v il1 low level input voltage ?0.3 0.3*v dd v for all input pins except reset , dbg, xin v il2 low level input voltage ?0.3 ? 0.2*v dd v for reset , dbg, and xin v ih1 high level input voltage 0.7*v dd ? 5.5 v port a, c, d, e, f, and g pins 1 except pins pc0 and pc1 v ih2 high level input voltage 0.7*v dd ?v dd +0.3 v port b, h and pins pc0 and pc1 v ih3 high level input voltage 0.8*v dd ?v dd +0.3 v reset , dbg, and xin pins v ol1 low level output voltage standard drive ??0.4vi ol = 2 ma; vdd = 3.0 v high output drive disabled v oh1 high level output voltage standard drive 2.4 ? ? v i oh = -2 ma; vdd = 3.0 v high output drive disabled v ol2 low level output voltage high drive ??0.6vi ol = 20 ma; vdd = 3.3 v high output drive enabled t a = -40 c to +70 c v oh2 high level output voltage high drive 2.4 ? ? v i oh = -20 ma; vdd = 3.3 v high output drive enabled; t a = -40 c to +70 c v ol3 low level output voltage high drive ??0.6vi ol = 15 ma; vdd = 3.3 v high output drive enabled; ta = +70 c to +125 c v oh3 high level output voltage high drive 2.4 ? ? v i oh = 15 ma; vdd = 3.3 v high output drive enabled; ta = +70 c to +125 c i il input leakage current ?5 v +5 av dd = 3.6 v; v in = vdd or vss 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 340 i tl tri-state leakage current ?5 ? +5 av dd = 3.6 v c pad gpio port pad capacitance ?8.0 2 ?pf c xin xin pad capacitance ? 8.0 2 ?pf c xout xout pad capacitance ? 9.5 2 ?pf i pu weak pull-up current 30 100 350 ma v dd = 2.7 v to 3.6 v i ccs1 supply current in stop mode with vbo enabled 600 a v dd = 3.0 v; 25 c i ccs2 supply current in stop mode with vbo disabled 2 a v dd = 3.0 v; 25 c i ccs3 supply current in stop mode with vbo disabled and wdt disabled 1 a v dd = 3.0 v; 25 c i cca active i dd at 20 mhz ? 18 35 ma typ: vdd=3.0 v/30 c max: vdd=3.6 v/125 c peripherals enabled, no loads i cch i dd in halt mode at 20 mhz ? 4 6 ma typ: vdd=3.0 v/30 c max: vdd=3.6 v/125 c peripherals off, no loads note 1. this condition excludes all pins that have on-chip pull-ups enabled, when driven low. table 183. dc characteristics (continued) symbol parameter t a = ?40 c to 125 c units conditions min typ max www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 341 figure 72 displays the typical current consumptio n while operating at 3.3 v at 30 oc versus the system clock frequency. figure 72. typical i dd versus system clock frequency active i dd vs clk freq at 30 oc 0 5 10 15 20 25 30 35 0 5 10 15 20 25 clk freq (mhz) active i dd (ma) vdd=2.6v vdd=3.0v vdd=3.3v vdd=3.7v www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 342 figure 73 displays typical current c onsumption while operating at 3.3 v at 30 oc in halt mode versus the system clock frequency. figure 73. typical halt mode i dd versus system clock frequency halt i dd vs clk freq at 30 oc 0 1 2 3 4 5 6 0 5 10 15 20 25 clk freq (m hz) i dd halt (ma) vdd=2.6v vdd=3.0v vdd=3.3v vdd=3.7v www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 343 figure 74 displays the stop mode cu rrent consumption versus v dd at ambient temperature with vbo and wdt disabled (i ccs2 ). figure 74. stop mode current versus v dd on-chip peripheral ac and dc electrical characteristics table 184 lists the por and vbo electri cal characteristics and timing. table 185 on page 344 lists the reset and stop mode recovery pin timing. table 184. por and vbo electrical characteristics and timing symbol parameter t a = ?40 c to 125 c units conditions min typ 1 max v por power-on reset voltage threshold 2.20 2.45 2.70 v v dd = v por v vbo voltage brownout reset voltage threshold 2.15 2.40 2.65 v v dd = v vbo v por ?v vbo 50 100 mv starting v dd voltage to ensure valid por ?v ss ?v stop i dd vs v dd at temperature 0 10 20 30 40 50 60 2.5 3 3.5 4 v dd (v) stop i dd (ua) -40c 0c 30c 70c 105c 125c www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 344 t ana power-on reset analog delay ?50?msv dd > v por ; t por digital reset delay follows t ana t por power-on reset digital delay ? 12 ? us 66 ipo cycles t vbo voltage brownout pulse rejection period ?10?msv dd < v vbo to generate a reset t ramp time for v dd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms i cc supply current 500 a v dd = 3.3 v. note 1. data in the typical column is from characterization at 3.3 v and 0 c. these values are provided for design guidance only and are not tested in production. table 185. reset and stop mode recovery pin timing symbol parameter t a = ?40 c to 125 c units conditions min typ max t reset reset pin assertion to initiate a system reset 4??t clk not in stop mode. t clk = system clock period. t smr stop mode recovery pin pulse rejection period 10 20 40 ns reset, dbg, and gpio pins configured as smr sources. table 184. por and vbo electrical characteristics and timing (continued) symbol parameter t a = ?40 c to 125 c units conditions min typ 1 max www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 345 table 186 list the flash memory electrica l characteristics and timing. table 187 on page 345 lists the wdt electri cal characteristics and timing. table 186. flash memory electrical characteristics and timing parameter v dd = 2.7 to 3.6 v t a = ?40 c to 125 c units notes min typ max flash byte read time 50 ? ? ns flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms writes to single address before next erase ?? 2 flash row program time ?? 8ms cumulative program time for single row cannot exceed limit before next erase 1 data retention 100 ? ? years 25 c endurance 10,000 ? ? cycles program/erase cycles note 1. this parameter is only an issue when bypassing the flash controller. table 187. watchdog timer electrical characteristics and timing symbol parameter t a = ?40 c to 125 c units conditions min typ max f wdt wdt oscillator frequency 51020khz www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 346 table 188 lists the analog-to-digital converter (adc) electrical characteristics and timing. table 188. adc electrical characteristics and timing symbol parameter t a = ?40 c to 125 c units conditions min typ max resolution 10 ? ? bits external v ref = 2.0 v throughput conversion 13 clks adc clock cycles adcclk frequency 20 mhz dnl differential non-linearity 1 ?0.99 2 lsb typical system config 2 inl integral non-linearity 1 ?3 3 lsb typical system config 2 offset error 1 ?30 30 mv typical system config 2 gain error 1 ?4.5 4.5 lsb typical system config 2 vref on-chip voltage reference 3 1.9 2 2.1 v externally supplied voltage reference avdd-1.0 v v analog input voltage range 0vrefv analog input current 500 na reference input current 2.0 ma worst case code analog input capacitance 15 pf avdd operating supply voltage 2.7 3.6 v operating current, avdd 9ma active conversion @ 20 mhz power down current <1 ua notes 1. these parameters are guaranteed by design and not tested on every part. 2. typical system configurat ion is defined as, 20 mhz clock wi th adc clock divide by 4, 1 us sample hold time, 0.5 us sample settling time. 3. on-chip voltage reference cannot be used if avdd is below 3.0 v. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 347 table 189 provides electrical characteristics and timing information for the on-chip comparator. table 190 provides electrical characteristics and timing information for the on-chip operational amplifier. table 189. comparator electrical characteristics symbol parameter t a = ?40 oc to 125 oc units conditions min typ max v coff input offset ?515mv v dd = 3.3 v; v in = v dd 2 t cprop propagation delay ?200 ns vcomm mode = 1 v vdiff = 100 mv i b input bias current 1a cmvr common-mode voltage range ?0.3 v dd ? 1 v i cc supply current 40 a v dd = 3.6 v t wup wake up time from off state 5s cinp = 0.9 v cinn= 1.0 v table 190. operational amplifier electrical characteristics symbol parameter t a = ?40 oc to 125 oc units conditions min typ max v os input offset 5 15 mv v dd =3.3 v; v cm = v dd 2 tc vos input offset average drift 1 v/c i b input bias current tbd ua i os input offset current tbd ua cmvr common-mode voltage range ?0.3 v dd ? 1 v v ol output low 0.1 v i sink = 100 a v oh output high v dd ? 1 v i source = 100 a cmrr common-mode rejection ratio 70 db 0 < v cm < 1.4 v; t a = 25 oc www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 348 psrr power supply rejection ratio 80 db v dd = 2.7 v ? 3.6 v; t a = 25 oc a vol voltage gain 80 db sr+ slew rate while rising 12 v/us r load = 33 k; c load = 50 pf; a vcl = 1, v in = 0.7 v to 1.7 v sr- slew rate while falling 16 v/us r load = 33 k; c load = 50 pf; a vcl = 1, v in = 1.7 v to 0.7 v gbw gain-bandwidth product 5 mhz fm phase margin 50 degree i s supply current 1 ma v dd = 3.6 v; v out = v dd 2 t wup wake up time from off state 20 us table 190. operational amplifier electrical characteristics (continued) symbol parameter t a = ?40 oc to 125 oc units conditions min typ max www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 349 ac characteristics the section provides information on the ac characteristics and tim ing. all ac timing information assumes a standard load of 50 pf on all outputs. table 191 lists the zneo Z16F series ac characteristics and timing. general purpose i/o port input data sample timing figure 75 displays timing of the gpio port in put sampling. the input value on a gpio port pin is sampled on the rising edge of the system clock. the port value is then available to the zneo cpu on the second rising clock ed ge following the change of the port value. table 192 lists the gpio port input timing. table 191. ac characteristics symbol parameter t a = ?40 c to 125 c units conditions min max f sysclk system clock frequency ? 20.0 mhz read-only from flash memory 0.032768 20.0 mhz program or erasure of the flash memory f xtal crystal oscillator frequency 1.0 20.0 mhz system clock frequencies below the crystal oscillator minimum require an external clock driver t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50 ns t xinl system clock low time 20 30 ns t clk = 50 ns t xinr system clock rise time ? 3 ns t clk = 50 ns t xinf system clock fall time ? 3 ns t clk = 50 ns www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 350 figure 75. port input sample timing on-chip debugger timing table 193 provide timing information for the dbg pin. the dbg pin timing specifications assume a 4 s maximum rise and fall time. table 192. gpio port input timing parameter abbreviation delay (ns) min max t smr gpio port pin pulse width to ensure stop mode recovery (for gpio port pins enabled as smr sources) 1 s table 193. on-chip debugger timing parameter abbreviation delay (ns) min max dbg dbg frequency system clock / 4 system tclk port pin port value changes to 0 0 value may be read from port input input value port input data register latch clock data register www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 351 spi master mode timing figure 76 and table 194 provides timing information for spi master mode pins. timing is shown with sck rising edge used to source mosi output data, sck falling edge used to sample miso input data. timing on the ss output pin(s) is controlled by software. figure 76. spi master mode timing table 194. spi master mode timing parameter abbreviation delay (ns) min max spi master t 1 sck rise to mosi output valid delay ?5 +5 t 2 miso input to sck (receive edge) setup time 20 t 3 miso input to sck (receive edge) hold time 0 sck mosi t1 (output) miso t2 t3 (input) output data input data www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 352 spi slave mode timing figure 77 and table 195 provide timing information for th e spi slave mode pins. timing is shown with sck rising edge used to sour ce miso output data, sck falling edge used to sample mosi input data. figure 77. spi slave mode timing table 195. spi slave mode timing parameter abbreviation delay (ns) min max spi slave t 1 sck (transmit edge) to miso output valid delay 2 * xin period 3 * xin period + 20 ns t 2 mosi input to sck (rec eive edge) setup time 0 t 3 mosi input to sck (receive edge) hold time 3 * xin period t 4 ss input assertio n to sck setup 1 * xin period sck miso t1 (output) mosi t2 t3 (input) output data input data ss (input) t4 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 353 i 2 c timing figure 78 and table 196 provide timing information for i 2 c pins. figure 78. i 2 c timing table 196. i 2 c timing parameter abbreviation delay (ns) min max i 2 c t 1 scl fall to sda output delay scl period/4 t 2 sda input to scl rising edge setup time 0 t 3 sda input to scl falling edge hold time 0 scl sda t1 (output) sda t2 (input) output data input data (output) t3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 354 uart timing figure 79 and table 197 provide timing information for uart pins for the case where the clear to send input pin (cts ) is used for flow control. in this example, it is assumed that the driver enable polarity has been configured to be active low and is represented here by de . the cts to de assertion delay (t1) assumes the uart transmit data register has been loaded with data prior to cts assertion. figure 79. uart timing with cts table 197. uart timing with cts parameter abbreviation delay (ns) min max t 1 cts fall to de assertion delay 2 * xin period 2 * xin period + 1 bit period t 2 de assertion to txd falling edge (start) delay 1 bit period 1 bit period + 1 * xin period t 3 end of stop bit(s) to de deassertion delay 1 * xin period 2 * xin period t 1 t 2 txd (output) de (output) cts (input) start bit 0 t 3 bit 7 parity stop bit 1 end of stop bit(s) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 355 figure 80 and table 198 provide timing information for uart pins for the case where the clear to send input signal (cts ) is not used for flow control. in this example, it is assumed that the driver enable polarity ha s been configured to be active low and is represented here by de . de asserts after the uart transmit data register has been written. de remains asserted for multiple characters as long as the transmit data register is written with the next character befo re the current character has completed. figure 80. uart timing without cts table 198. uart timing without cts parameter abbreviation delay (ns) min max t 1 de assertion to txd falling edge (start) delay 1 bit period 1 bit period + 1 * xin period t 2 end of stop bit(s) to de deassertion delay 1 * xin period 2 * xin period t 1 txd (output) de (output) start bit 0 t 2 bit 7 parity stop bit 1 end of stop bit(s) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y electrical characteristics zneo ? Z16F series product specification 356 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary packaging zneo ? Z16F series product specification 357 packaging figure 81 displays the 64-pin low-profile quad flat package (lqfp) available for the zneo ? Z16F series devices. figure 81. 64-pin low-profile quad flat package (lqfp) figure 82 displays the 68-pin plastic lead chip carrier (plcc) package available for the zneo Z16F series devices. figure 82. 68-pin plastic lead chip carrier (plcc) package c a1 a2 a le e he e 0-7 l b hd d detail a www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary packaging zneo ? Z16F series product specification 358 figure 83 displays the 80-pin quad flat pack age (qfp) available for the zneo Z16F series devices. figure 83. 80-pin quad-flat package (qfp) a2 e he 1 80 b detail a 0-10 l e 24 25 detail a hd d 65 64 40 41 17.70 he 18.15 .715 .697 .004" controlling dimensions : millimeter l e e c lead coplanarity : max .10 notes: 2. 0.80 bsc 0.70 13.90 1.10 14.10 .028 .043 .0315 bsc .547 .555 a1 d hd c b a2 symbol a1 19.90 23.70 0.13 2.60 0.30 0.10 20.10 24.15 0.20 0.38 2.80 0.45 millimeter min max .783 .933 .005 .791 .951 .008 .102 .012 .004 .110 .018 .015 inch min max www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary packaging zneo ? Z16F series product specification 359 figure 84 displays the 100-pin low-profile quad -flat package (lqfp) available for the zneo Z16F series devices. figure 84. 100-pin low-profile quad-flat package (lqfp) 20984 05-07-05 m. fonte www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary packaging zneo ? Z16F series product specification 360 ordering information table 199 identifies the basic features and package styles available for each device within the zneo product line. table 199. zneo part selection guide part number flash (kb) ram (kb) external interface i/o multi-channel timers with pwm standard timers with pwm adc inputs uarts with lin and irda i 2 c master/slave espi 64/68-pin packages 80-pin package 100-pin package Z16F2811 128 4 yes 76 1 3 12 2 1 1 x 1284yes601 3122 1 1 x Z16F2810 128 4 no 60 1 3 12 2 1 1 x 128 4 no 46 1 3 12 2 1 1 x Z16F6411 64 4 yes 76 1 3 12 2 1 1 x 64 4 yes 60 1 3 12 2 1 1 x Z16F3211 32 2 yes 76 1 3 12 2 1 1 x 32 2 yes 60 1 3 12 2 1 1 x www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary packaging zneo ? Z16F series product specification 361 you can order the zneo Z16F series from zilog ? by providing the part numbers listed in the table below . for more information regarding orderi ng, contact your local zilog sales office. our website ( www.zilog.com ) lists all regional office s and provides additional information on zneo Z16F series product. part number flash (kbytes) ram (kbytes) external interface i/o multi-channel timers with pwm standard timers with pwm adc inputs i 2 c master/slave uart with lin and irda espi package zneo Z16F series standard temperature: 0 c to +70 c Z16F2811al20sg 128 4 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F2811fi20sg 128 4 yes 60 1 3 12 1 2 1 80-pin qfp Z16F2810fi20sg 128 4 no 60 1 3 12 1 2 1 80-pin qfp Z16F2810ag20sg 128 4 no 46 1 3 12 1 2 1 64-pin lqfp Z16F2810vh20sg 128 4 no 46 1 3 12 1 2 1 68-pin plcc Z16F6411al20sg 64 4 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F6411fi20sg 64 4 yes 60 1 3 12 1 2 1 80-pin qfp Z16F3211al20sg 32 2 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F3211fi20sg 32 2 yes 60 1 3 12 1 2 1 80-pin qfp extended temperature: ?40 c to +105 c Z16F2811al20eg 128 4 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F2811fi20eg 128 4 yes 60 1 3 12 1 2 1 80-pin qfp Z16F2810fi20eg 128 4 no 60 1 3 12 1 2 1 80-pin qfp Z16F2810ag20eg 128 4 no 46 1 3 12 1 2 1 64-pin lqfp Z16F2810vh20eg 128 4 no 46 1 3 12 1 2 1 68-pin plcc Z16F6411al20eg 64 4 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F6411fi20eg 64 4 yes 60 1 3 12 1 2 1 80-pin qfp Z16F3211al20eg 32 2 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F3211fi20eg 32 2 yes 60 1 3 12 1 2 1 80-pin qfp automotive temperature: ?40 c to +125 c Z16F2811al20ag 128 4 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F2811fi20ag 128 4 yes 60 1 3 12 1 2 1 80-pin qfp www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary packaging zneo ? Z16F series product specification 362 Z16F2810fi20ag 128 4 no 60 1 3 12 1 2 1 80-pin qfp Z16F2810ag20ag 128 4 no 46 1 3 12 1 2 1 64-pin lqfp Z16F2810vh20ag 128 4 no 46 1 3 12 1 2 1 68-pin plcc Z16F6411al20ag 64 4 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F6411fi20ag 64 4 yes 60 1 3 12 1 2 1 80-pin qfp Z16F3211al20ag 32 2 yes 76 1 3 12 1 2 1 100-pin lqfp Z16F3211fi20ag 32 2 yes 60 1 3 12 1 2 1 80-pin qfp zneo Z16F series development tools Z16F2800100zcog zneo ? Z16F series development kit zusbsc00100zacg usb smart cable accessory kit zusboptsc01zacg opto-isolated usb smart cable accessory kit zenetsc0100zacg ethernet smart cable accessory kit part number flash (kbytes) ram (kbytes) external interface i/o multi-channel timers with pwm standard timers with pwm adc inputs i 2 c master/slave uart with lin and irda espi package www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary packaging zneo ? Z16F series product specification 363 part number suffix designations z16 f 28 11 al 20 s g environmental flow g = lead free temperature range s = standard, 0 c to +70 c e = extended, ?40 c to +105 c a = automotive, ?40 c to +125 c speed 20 = 20 mhz package ag = lqfp-64 al = lqfp-100 fi = qfp-80 vh = plcc-68 device type 10 = without external interface 11 = with external interface memory size 28 = 128 kb flash 64 = 64 kb flash 32 = 32 kb flash memory type f = flash zilog ? 16-bit zneo microcontroller family note : the packages are not available for all memory sizes. see ordering information for the packages available as per your requirements. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary packaging zneo ? Z16F series product specification 364 pre-characterization product the product represented by this document is newly introduced and zilog ? has not completed the full characterization of the prod uct. the document states what zilog knows about this product at this time, but additi onal features or nonconformance with some aspects of the document might be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery might be uncertain at times, due to start-up yi eld issues. for more in formation, please visit www.zilog.com . www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y index zneo ? Z16F series product specification 365 index numerics 10-bit adc 4 68-pin plastic lead chip carrier package (plcc) 355 64-lead low-profile quad flat package 355 68-lead plastic lead chip carrier package 355 80-lead quad flat package 356, 357 a absolute maximum ratings 335 ac characteristics 347 adc block diagram 241 electrical characteris tics and timing 344 overview 242 adc channel register 1 (adcctl) 245 adc data high byte register (adcdh) 246, 250 adc data low bit re gister (adcdl) 247, 248, 249, 250, 251 analog block/pwm signa l synchronization 243 analog block/pwm signa l zynchronization 243 analog signals 14 analog-to-digital converter overview 242 architecture voltage measurements 242 b baud rate generator, uart 148 block diagram 2 bus width 19 bus width non-volatile memory (internal) 23 ram (internal) 23 c characteristics, electrical 335 clock phase (spi) 178 comparator definition 251 non-inverting/inverting input 252 operation 252 control register external interface 44, 283 control register definition, uart 151 control register, i2c 227 control registers cpu 21 cpu control registers 21 cpu and peripheral overview 3 current measurement architecture 242 operation 242 customer support 370 d data width 19 data register, i2c 225 dc characteristics 337 debugger, on-chip 297 device, port availability 67 dma controller 4 e electrical characteristics 335 adc 344 flash memory and timing 343 gpio input data sample timing 347 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y index zneo ? Z16F series product specification 366 watchdog timer 343 electrical noise 242 external interface 39 control register 44, 283 isa-compatible mode 43 operation 42 signals 39, 288 external memory 19 external pin reset 61 f flash controller 4 option bit address space 291 option bit configuration - reset 291 program memory address 0000h 292 program memory address 0001h 293, 294 flash memory 255 arrangement 256 code protection 257 configurations 255 control register definitions 261 controller bypass 260 electrical characteris tics and timing 343 flash status register 261 mass erase 260 operation 257 operation timing 257 page erase 259 page select register 263 fps register 263 fstat register 261 g general-purpose i/o 67 generator, wait state 42 gpio 4, 67 alternate functions 68 architecture 67 input data sample timing 347 interrupts 72 port a-h alternate function sub-registers 74 port a-h data direction sub-registers 73 port a-h input data registers 72 port a-h output contro l sub-registers 74, 76 port a-h output data registers 72 port a-h stop mode reco very sub-registers 76, 77, 78 port availability by device 67 port input timing 348 h halt mode 65 i i/o memory 19 precautions 21 i2c 4 10-bit address read transaction 213 10-bit address transaction 210 10-bit addressed slave da ta transfer format 210, 217 7-bit address tr ansaction 207, 215 7-bit address, reading a transaction 212 7-bit addressed slave da ta transfer format 209, 216 7-bit receive data transfer format 213, 218, 220 baud high and low byt e registers 228, 229, 233, 235 c status register 225, 229 control register definitions 225 controller 201, 241 controller signals 13 interrupts 204 operation 204 sda and scl signals 204 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y index zneo ? Z16F series product specification 367 stop and start conditions 206 i2cbrh register 228, 230, 233, 235 i2cbrl register 229 i2cctl register 227 i2cdata register 225 i2cstat register 225, 229 infrared encoder/decoder (irda) 169 interface, external 39 interrupt controller 4, 79 architecture 80 interrupt assertion types 83 interrupt vectors and priority 83 operation 82 register definitions 84 interrupt request 0 register 85 interrupt request 1 register 87 interrupt request 2 register 88 interrupt vector listing 80 interrupts spi 187 uart 145 introduction 1 irda architecture 149, 169 block diagram 149, 169 control register definitions 172 operation 150, 169 receiving data 171 transmitting data 170 irq0 enable high and low bit registers 89 irq1 enable high and low bit registers 91 irq2 enable high and low bit registers 92 isa-compatible mode 43 l low power modes 65 lqfp 64 lead 355 m master interrupt enable 82 master-in, slave-out and-in 175 memory bus widths 19 external 19 i/o 19 internal 19, 20, 21 map 19 non-volatile 19, 20 parallel access 19 ram 19, 21 random access 19, 21 memory access quad 23 word 23 memory map 19 miso 175 mode isa-compatible 43 mosi 175 motor control measurements adc control register definitions 244 interrupts 244 overview 242 multiprocessor mode, uart 140 n noise, electrical 242 non-volatile memory 19, 20 bus width 23 o ocd architecture 297 baud rate limits 300 block diagram 297 commands 308 timing 348 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y index zneo ? Z16F series product specification 368 on-chip debugger 4 on-chip debugger (ocd) 297 on-chip debugger signals 15 on-chip oscillator 325 operation 243 current measurement 242 voltage measurement timing diagram 243 operational amplifier operation 252 overview 251 operational descri ption 95, 113, 133, 329, 333 option bits 20 oscillator signals 15 p packaging lqfp 64 lead 355 plcc 68 lead 355 qfp 356, 357 parallel access memory 19 peripheral ac and dc el ectrical characteristics 341 memory internal 19 phase=0 timing (spi) 179 phase=1 timing (spi) 180 pin characteristics 16 plcc 68-lead 355 port availability, device 67 port input timing (gpio) 348 power supply signals 15 power-on and voltage brown-out 341 precautions, i/o memory 21 q qfp 356, 357 quad mode memory access 23 r ram 19, 21 bus width 23 random-access memory 19, 21 receive 7-bit data transfer format (i2c) 213, 218, 220 irda data 171 receiving uart data-int errupt-driven method 138 receiving uart data-polled method 137 register 193 baud low and high byte (i2c) 228, 229, 233, 235 baud rate high and low byte (spi) 198 control (spi) 191 control, i2c 227 data, spi 189, 190 external interface control 44, 283 flash page select (fps) 263 flash status (fstat) 261 gpio port a-h altern ate function sub-reg- isters 74, 75 gpio port a-h data di rection sub-registers 73 i2c baud rate high (i2cbrh) 228, 230, 233, 235 i2c control (i2cctl) 227 i2c data (i2cdata) 225 i2c status 225, 229 i2c status (i2cstat) 225, 229 i2cbaud rate low (i2cbrl) 229 mode, spi 193 spi baud rate high byte (spibrh) 198 spi baud rate low byte (spibrl) 199 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y index zneo ? Z16F series product specification 369 spi control (spictl) 191 spi data (spidata) 190 spi status (spistat) 195 status, spi 195 uartx baud rate high byte (uxbrh) 162 uartx baud rate low byte (uxbrl) 163 uartx control 0 (uxctl0) 157, 162 uartx control 1 (uxctl1) 158, 160 uartx receive data (uxrxd) 151 uartx status 0 (uxstat0) 152, 153 uartx status 1 (uxstat1) 155 uartx transmit data (uxtxd) 151 watchdog timer control (wdtctl) 331, 332 watchdog timer reload high byte (wdth) 240 watchdog timer reload low byte (wdtl) 240 register file address map 25 registers adc channel 1 245 adc data high byte 246, 250 adc data low bit 247, 248, 249, 250, 251 reset and stop mode characteristics 57 and stop mode recovery 57 controller 4 s sck 175 sda and scl (irda) signals 204 serial clock 175 serial peripheral interface (spi) 173 signal descriptions 12 sio 4 slave data transfer formats (i2c) 210, 217 slave select 175 spi architecture 173 baud rate generator 189 baud rate high and low byte register 198 clock phase 178 configured as slave 186 control register 191 control register definitions 189 data register 189, 190 error detection 186 interrupts 187 mode fault error 186 mode register 193 multi-master operation 183 operation 175 overrun error 186, 187 signals 175 single master, multiple slave system 184 single master,single slave system 184 status register 195 timing, phase = 0 179 timing, phase=1 180 spi controller signals 13 spi mode (spimode) 193 spibrh register 198 spibrl register 199 spictl register 191 spidata register 190 spimode register 193 spistat register 195 ss, spi signal 175 stop mode 65 stop mode recovery sources 61 using a gpio port pin transition 62 using watchdog timer time-out 62 system 20 system and core resets 58 system vectors 20 t tiing diagram, volta ge measurement 243 timer signals 14 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y index zneo ? Z16F series product specification 370 timers 4, 95 architecture 95, 113 block diagram 95, 114 capture mode 101, 102 capture/compare mode 102 compare mode 103 continuous mode 98 counter mode 99 gated mode 104 one-shot mode 96 operating mode 96 pwm mode 100 reading the timer count values 104 reload high and low byte registers 106, 121 timer control register definitions 105, 120 triggered one-shot mode 97 timers 0-3 control registers 107, 109 high and low byte registers 105, 106, 120, 122 timing diagram, voltage measurement 243 transmit irda data 170 transmitting uart data-polled method 135 u uart 4 architecture 134 asynchronous data fo rmat without/with parity 135 baud rate generator 148 baud rates table 165 control register definitions 151 controller signals 14 data format 135 interrupts 145 multiprocessor mode 140 receiving data using interrupt-driven meth- od 138 receiving data using the polled method 137 transmitting data us ing the polled method 135 x baud rate high and low registers 162 x control 0 and cont rol 1 registers 157, 158 x status 0 and status 1 registers 152, 155 uxbrh register 162 uxbrl register 163 uxctl0 register 157, 162 uxctl1 register 158, 160 uxrxd register 151 uxstat0 register 152, 153 uxstat1 register 155 uxtxd register 151 v vectors 20 interrupts 20 system exceptions 20 voltage brownout reset (vbr) 59 voltage measurement timing diagram 243 w wait state generator 42 watchdog timer approximate time-out delays 333 control register 331, 332 interrupt in stop mode 238 operation 333 refresh 238 reload unlock sequence 239 reload upper, high and low registers 240 reset 60 reset in normal operation 239 reset in stop mode 239 time-out response 238 watchdog timer approximate time-out delay 238 electrical characteristics and timing 343 interrupt in normal operation 238 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 p r e l i m i n a r y index zneo ? Z16F series product specification 371 wdtctl register 331, 332 wdth register 240 wdtl register 240 word mode memory access 23 z zneo block diagram 2 introduction 1 zneo cpu features 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ps022007-0109 preliminary customer support zneo ? Z16F series product specification 372 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offerings, please visit zilog?s knowledge base at http://www.zilog.com/kb . for any comments, detail technical questions, or reporting problems, please visit zilog?s technical support at http://support.zilog.com . www.datasheet.net/ datasheet pdf - http://www..co.kr/ |
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